From: Simon Dardis Date: Fri, 16 Sep 2016 13:50:43 +0000 (+0000) Subject: [mips] Fix aui/daui/dahi/dati for MIPSR6 X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=e38b67fe3ba7106df4d0d232293ac67649f547fd;p=llvm [mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281724 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index cdbf4a62c8c..600316acaeb 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3824,6 +3824,8 @@ MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst, return Match_Success; case Mips::DATI: case Mips::DAHI: + case Mips::DATI_MM64R6: + case Mips::DAHI_MM64R6: if (static_cast(*Operands[1]) .isValidForTie(static_cast(*Operands[2]))) return Match_Success; @@ -3832,6 +3834,14 @@ MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst, } unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { switch (Inst.getOpcode()) { + // As described by the MIPSR6 spec, daui must not use the zero operand for + // its source operand. + case Mips::DAUI: + case Mips::DAUI_MM64R6: + if (Inst.getOperand(1).getReg() == Mips::ZERO || + Inst.getOperand(1).getReg() == Mips::ZERO_64) + return Match_RequiresNoZeroRegister; + return Match_Success; // As described by the Mips32r2 spec, the registers Rd and Rs for // jalr.hb must be different. // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index f53998ea8e7..74a8f4f2152 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -438,6 +438,14 @@ template static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder); +template +static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + +template +static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + template static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, @@ -595,6 +603,34 @@ static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, return MCDisassembler::Success; } +template +static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder) { + InsnType Rt = fieldFromInstruction(insn, 16, 5); + InsnType Imm = fieldFromInstruction(insn, 0, 16); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, + Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, + Rt))); + MI.addOperand(MCOperand::createImm(Imm)); + + return MCDisassembler::Success; +} + +template +static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder) { + InsnType Rt = fieldFromInstruction(insn, 21, 5); + InsnType Imm = fieldFromInstruction(insn, 0, 16); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, + Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, + Rt))); + MI.addOperand(MCOperand::createImm(Imm)); + + return MCDisassembler::Success; +} + template static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index b8d8aa0ce20..913074ba15a 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -567,7 +567,7 @@ class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2, class AUI_MMR6_DESC_BASE : MMR6Arch { dag OutOperandList = (outs GPROpnd:$rt); - dag InOperandList = (ins GPROpnd:$rs, simm16:$imm); + dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm"); list Pattern = []; InstrItinClass Itinerary = Itin; diff --git a/lib/Target/Mips/MicroMips64r6InstrInfo.td b/lib/Target/Mips/MicroMips64r6InstrInfo.td index 508b34299bb..1f152d0e190 100644 --- a/lib/Target/Mips/MicroMips64r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips64r6InstrInfo.td @@ -81,7 +81,7 @@ class DAUI_MMR6_DESC_BASE : MMR6Arch, MipsR6Inst { dag OutOperandList = (outs GPROpnd:$rt); - dag InOperandList = (ins GPROpnd:$rs, simm16:$imm); + dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm"); list Pattern = []; InstrItinClass Itinerary = Itin; @@ -92,8 +92,8 @@ class DAHI_DATI_DESC_BASE : MMR6Arch, MipsR6Inst { dag OutOperandList = (outs GPROpnd:$rs); - dag InOperandList = (ins GPROpnd:$rt, simm16:$imm); - string AsmString = !strconcat(instr_asm, "\t$rt, $imm"); + dag InOperandList = (ins GPROpnd:$rt, uimm16:$imm); + string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm"); string Constraints = "$rs = $rt"; InstrItinClass Itinerary = Itin; } @@ -360,8 +360,10 @@ class LWUPC_MM64R6_DESC { let DecoderNamespace = "MicroMipsR6" in { def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6; - def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6; - def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6; + let DecoderMethod = "DecodeDAHIDATIMMR6" in { + def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6; + def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6; + } def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC, ISA_MICROMIPS64R6; def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC, diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index e81869513b6..34e3936b3cd 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -324,7 +324,7 @@ class AUI_DESC_BASE : MipsR6Arch { dag OutOperandList = (outs GPROpnd:$rs); - dag InOperandList = (ins GPROpnd:$rt, simm16:$imm); + dag InOperandList = (ins GPROpnd:$rt, uimm16:$imm); string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm"); list Pattern = []; InstrItinClass Itinerary = itin; diff --git a/lib/Target/Mips/Mips64r6InstrInfo.td b/lib/Target/Mips/Mips64r6InstrInfo.td index c380dfdc480..dabf4e0a52e 100644 --- a/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/lib/Target/Mips/Mips64r6InstrInfo.td @@ -48,8 +48,8 @@ class SCD_R6_ENC : SPECIAL3_LL_SC_FM; class AHI_ATI_DESC_BASE { dag OutOperandList = (outs GPROpnd:$rs); - dag InOperandList = (ins GPROpnd:$rt, simm16_relaxed:$imm); - string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm"); + dag InOperandList = (ins GPROpnd:$rt, uimm16_altrelaxed:$imm); + string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm"); string Constraints = "$rs = $rt"; InstrItinClass Itinerary = itin; } @@ -111,8 +111,10 @@ class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>; //===----------------------------------------------------------------------===// let AdditionalPredicates = [NotInMicroMips] in { - def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6; - def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6; + let DecoderMethod = "DecodeDAHIDATI" in { + def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6; + def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6; + } def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6; def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6; def DBITSWAP : R6MMR6Rel, DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 39b31074608..131a7519d3c 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -507,6 +507,14 @@ def UImm16RelaxedAsmOperandClass let PredicateMethod = "isAnyImm<16>"; let DiagnosticType = "UImm16_Relaxed"; } +// Similar to the relaxed classes which take an SImm and render it as +// an UImm, this takes a UImm and renders it as an SImm. +def UImm16AltRelaxedAsmOperandClass + : SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> { + let Name = "UImm16_AltRelaxed"; + let PredicateMethod = "isUImm<16>"; + let DiagnosticType = "UImm16_AltRelaxed"; +} def UImm16AsmOperandClass : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>; def SImm16RelaxedAsmOperandClass @@ -515,6 +523,7 @@ def SImm16RelaxedAsmOperandClass let PredicateMethod = "isAnyImm<16>"; let DiagnosticType = "SImm16_Relaxed"; } + def SImm16AsmOperandClass : SImmAsmOperandClass<16, [SImm16RelaxedAsmOperandClass]>; def ConstantSImm10Lsl3AsmOperandClass : AsmOperandClass { @@ -785,6 +794,11 @@ def uimm16_64_relaxed : Operand { !cast("UImm16RelaxedAsmOperandClass"); } +def uimm16_altrelaxed : Operand { + let PrintMethod = "printUImm<16>"; + let ParserMatchClass = + !cast("UImm16AltRelaxedAsmOperandClass"); +} // Like uimm5 but reports a less confusing error for 32-63 when // an instruction alias permits that. def uimm5_report_uimm6 : Operand { diff --git a/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/test/MC/Disassembler/Mips/micromips32r6/valid.txt index b84b16045db..26a1e6247bf 100644 --- a/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ b/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -38,7 +38,7 @@ 0x00 0x43 0x24 0x1f # CHECK: align $4, $2, $3, 2 0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5 0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234 -0x10 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 +0x10 0x62 0xff 0xe9 # CHECK: aui $3, $2, 65513 0x74 0x83 0x00 0x04 # CHECK: beqc $3, $4, 20 0xf4 0x83 0x00 0x04 # CHECK: bgec $3, $4, 20 0xc0 0x83 0x00 0x04 # CHECK: bgeuc $3, $4, 20 diff --git a/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/test/MC/Disassembler/Mips/micromips64r6/valid.txt index d29133045f2..5c70b5467bb 100644 --- a/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ b/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -35,8 +35,8 @@ 0x00 0x00 0x8b 0x7c # CHECK: syscall 0x01 0x8c 0x8b 0x7c # CHECK: syscall 396 0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5 -0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4 -0x42 0x03 0x00 0x04 # CHECK: dati $3, 4 +0x42 0x23 0x00 0x04 # CHECK: dahi $3, $3, 4 +0x42 0x03 0x00 0x04 # CHECK: dati $3, $3, 4 0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7 0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 39 0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7 diff --git a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt index 34bfd769f2d..ed6d75fe65b 100644 --- a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt +++ b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt @@ -4,7 +4,7 @@ 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56 -0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23 +0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, 65513 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1 0x9b 0x14 0x11 0x04 # CHECK: bal 21104 0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260 diff --git a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt index 7266848706d..c75cf389ed2 100644 --- a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt +++ b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt @@ -60,7 +60,7 @@ 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 -0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 +0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, 65513 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt index cda52962483..e8fc9a09b0f 100644 --- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt +++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt @@ -4,7 +4,7 @@ 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4 -0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23 +0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, 65513 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1 0x9b 0x14 0x11 0x04 # CHECK: bal 21104 0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260 @@ -95,6 +95,7 @@ 0x81 0x18 0xa4 0x46 # CHECK: cmp.un.d $f2, $f3, $f4 0x81 0x18 0x84 0x46 # CHECK: cmp.un.s $f2, $f3, $f4 0x78 0x56 0x66 0x04 # CHECK: dahi $3, $3, 22136 +0xcd 0xab 0x7e 0x04 # CHECK: dati $3, $3, 43981 0x64 0x23 0x43 0x7c # CHECK: dalign $4, $2, $3, 5 0x34 0x12 0x62 0x74 # CHECK: daui $3, $2, 4660 0x24 0x20 0x02 0x7c # CHECK: dbitswap $4, $2 diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt index 7be3fa71b1e..a047f6e4849 100644 --- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt +++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt @@ -51,7 +51,7 @@ 0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra 0x04 0x11 0x14 0x9b # CHECK: bal 21104 0x04 0x66 0x56 0x78 # CHECK: dahi $3, $3, 22136 -0x04 0x7e 0xab 0xcd # CHECK: dati $3, $3, -21555 +0x04 0x7e 0xab 0xcd # CHECK: dati $3, $3, 43981 # The encode/decode functions are not inverses of each other in the immediate case. 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336 0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20 @@ -77,7 +77,7 @@ 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 -0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 +0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, 65513 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3 0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0 diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s index c3a9153e241..3323803212b 100644 --- a/test/MC/Mips/micromips32r6/valid.s +++ b/test/MC/Mips/micromips32r6/valid.s @@ -19,7 +19,7 @@ andi $3, $4, 1234 # CHECK: andi $3, $4, 1234 # encoding: [0xd0,0x64,0x04,0xd2] auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0x78,0x7e,0xff,0xff] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x00,0x43,0x24,0x1f] - aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x10,0x62,0xff,0xe9] + aui $3,$2,23 # CHECK: aui $3, $2, 23 # encoding: [0x10,0x62,0x00,0x17] beqc $3,$4, 16 # CHECK: beqc $3, $4, 16 # encoding: [0x74,0x83,0x00,0x04] bgec $3,$4, 16 # CHECK: bgec $3, $4, 16 # encoding: [0xf4,0x83,0x00,0x04] bgeuc $3,$4, 16 # CHECK: bgeuc $3, $4, 16 # encoding: [0xc0,0x83,0x00,0x04] diff --git a/test/MC/Mips/micromips64r6/invalid.s b/test/MC/Mips/micromips64r6/invalid.s index a6aa5340051..861c55a6f83 100644 --- a/test/MC/Mips/micromips64r6/invalid.s +++ b/test/MC/Mips/micromips64r6/invalid.s @@ -19,6 +19,17 @@ bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate + dahi $4, $4, 65536 # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate + dahi $4, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate + dahi $4, $5, 1 # CHECK: :[[@LINE]]:3: error: source and destination must match + dati $4, $4, 65536 # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate + dati $4, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate + dati $4, $5, 1 # CHECK: :[[@LINE]]:3: error: source and destination must match + daui $4, $0, 1 # CHECK: :[[@LINE]]:3: error: invalid operand ($zero) for instruction + daui $4, $4, 65536 # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate + daui $4, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate + dati $4, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate + dati $4, $5, 1 # CHECK: :[[@LINE]]:3: error: source and destination must match # FIXME: Check various 'pos + size' constraints on dext* dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate @@ -399,5 +410,5 @@ lwupc $2, -262145 # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4 lwupc $2, $2 # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4 lwupc $2, bar+267 # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4 - aui $3, $4, 32768 # CHECK: :[[@LINE]]:15: error: expected 16-bit signed immediate - aui $3, $4, -32769 # CHECK: :[[@LINE]]:15: error: expected 16-bit signed immediate + aui $3, $4, -32768 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate + aui $3, $4, -32769 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate diff --git a/test/MC/Mips/micromips64r6/valid.s b/test/MC/Mips/micromips64r6/valid.s index e04bee45f4f..c07d7fd081f 100644 --- a/test/MC/Mips/micromips64r6/valid.s +++ b/test/MC/Mips/micromips64r6/valid.s @@ -16,9 +16,10 @@ a: bc16 132 # CHECK: bc16 132 # encoding: [0xcc,0x42] beqzc16 $6, 20 # CHECK: beqzc16 $6, 20 # encoding: [0x8f,0x0a] bnezc16 $6, 20 # CHECK: bnezc16 $6, 20 # encoding: [0xaf,0x0a] + aui $4, $5, 1 # CHECK: aui $4, $5, 1 # encoding: [0x10,0x85,0x00,0x01] daui $3, $4, 5 # CHECK: daui $3, $4, 5 # encoding: [0xf0,0x64,0x00,0x05] - dahi $3, 4 # CHECK: dahi $3, 4 # encoding: [0x42,0x23,0x00,0x04] - dati $3, 4 # CHECK: dati $3, 4 # encoding: [0x42,0x03,0x00,0x04] + dahi $3, $3, 4 # CHECK: dahi $3, $3, 4 # encoding: [0x42,0x23,0x00,0x04] + dati $3, $3, 4 # CHECK: dati $3, $3, 4 # encoding: [0x42,0x03,0x00,0x04] dext $9, $6, 3, 7 # CHECK: dext $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xec] dextm $9, $6, 3, 39 # CHECK: dextm $9, $6, 3, 39 # encoding: [0x59,0x26,0x30,0xe4] dextu $9, $6, 35, 7 # CHECK: dextu $9, $6, 35, 7 # encoding: [0x59,0x26,0x30,0xd4] diff --git a/test/MC/Mips/mips32r6/invalid.s b/test/MC/Mips/mips32r6/invalid.s index 287a99f2a8f..6cb4470fec9 100644 --- a/test/MC/Mips/mips32r6/invalid.s +++ b/test/MC/Mips/mips32r6/invalid.s @@ -10,6 +10,8 @@ local_label: .set noat align $4, $2, $3, -1 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate + aui $4, $4, 65536 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate + aui $4, $4, -1 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index cd90fcd279b..12b3459129b 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -20,7 +20,7 @@ a: addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] - aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] + aui $3, $2, 23 # CHECK: aui $3, $2, 23 # encoding: [0x3c,0x62,0x00,0x17] auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] diff --git a/test/MC/Mips/mips64r6/invalid.s b/test/MC/Mips/mips64r6/invalid.s index 1fdcca9f440..e79bb52ec90 100644 --- a/test/MC/Mips/mips64r6/invalid.s +++ b/test/MC/Mips/mips64r6/invalid.s @@ -10,6 +10,8 @@ local_label: .set noat align $4, $2, $3, -1 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate + aui $4, $4, 65536 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate + aui $4, $4, -1 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -110,8 +112,19 @@ local_label: bnezc $2, 4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + dahi $4, $4, 65536 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate + dahi $4, $4, -1 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate + dahi $4, $5, 1 # CHECK: :[[@LINE]]:9: error: source and destination must match dalign $4, $2, $3, -1 # CHECK: :[[@LINE]]:29: error: expected 3-bit unsigned immediate dalign $4, $2, $3, 8 # CHECK: :[[@LINE]]:29: error: expected 3-bit unsigned immediate + dati $4, $4, 65536 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate + dati $4, $4, -1 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate + dati $4, $5, 1 # CHECK: :[[@LINE]]:9: error: source and destination must match + daui $4, $0, 1 # CHECK: :[[@LINE]]:9: error: invalid operand ($zero) for instruction + daui $4, $4, 65536 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate + daui $4, $4, -1 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate + dati $4, $4, -1 # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate + dati $4, $5, 1 # CHECK: :[[@LINE]]:9: error: source and destination must match dlsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 dlsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index b92fd09f310..6ec347aca10 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -20,7 +20,7 @@ a: align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] - aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] + aui $3, $2, 23 # CHECK: aui $3, $2, 23 # encoding: [0x3c,0x62,0x00,0x17] auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] @@ -101,12 +101,12 @@ a: cmp.ult.s $f2,$f3,$f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x85] cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81] cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81] - daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f] - daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f] - dahi $3,$3,0x5678 # CHECK: dahi $3, $3, 22136 # encoding: [0x04,0x66,0x56,0x78] - dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64] - dati $3,$3,0xabcd # CHECK: dati $3, $3, -21555 # encoding: [0x04,0x7e,0xab,0xcd] - daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34] + daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f] + daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f] + dahi $3, $3, 0x5678 # CHECK: dahi $3, $3, 22136 # encoding: [0x04,0x66,0x56,0x78] + dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64] + dati $3, $3, 0xabcd # CHECK: dati $3, $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd] + daui $3, $2, 0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34] dbitswap $4, $2 # CHECK: dbitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x24] dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53] dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]