From: Marek Olsak <marek.olsak@amd.com>
Date: Fri, 25 Nov 2016 16:03:06 +0000 (+0000)
Subject: Revert "AMDGPU: Remove m0 spilling code"
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=e2c9a9f4aa14d94451681d9c1c6bc06842c84155;p=llvm

Revert "AMDGPU: Remove m0 spilling code"

This reverts commit f18de36554eb22416f8ba58e094e0272523a4301.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287931 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 93c2060381d..0ba76c7c8bb 100644
--- a/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -527,8 +527,6 @@ void SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
 
   bool SpillToSMEM = ST.hasScalarStores() && EnableSpillSGPRToSMEM;
 
-  assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
-
   const unsigned EltSize = 4;
 
   // SubReg carries the "Kill" flag when SubReg == SuperReg.
@@ -538,6 +536,19 @@ void SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
       SuperReg : getSubReg(SuperReg, getSubRegFromChannel(i));
 
     if (SpillToSMEM) {
+      if (SuperReg == AMDGPU::M0) {
+        assert(NumSubRegs == 1);
+        unsigned CopyM0
+          = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
+
+        BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), CopyM0)
+          .addReg(AMDGPU::M0, getKillRegState(IsKill));
+
+        // The real spill now kills the temp copy.
+        SubReg = SuperReg = CopyM0;
+        IsKill = true;
+      }
+
       int64_t FrOffset = FrameInfo.getObjectOffset(Index);
       unsigned Align = FrameInfo.getObjectAlignment(Index);
       MachinePointerInfo PtrInfo
@@ -575,6 +586,18 @@ void SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
     struct SIMachineFunctionInfo::SpilledReg Spill =
       MFI->getSpilledReg(MF, Index, i);
     if (Spill.hasReg()) {
+      if (SuperReg == AMDGPU::M0) {
+        assert(NumSubRegs == 1);
+        unsigned CopyM0
+          = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
+        BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), CopyM0)
+          .addReg(SuperReg, getKillRegState(IsKill));
+
+        // The real spill now kills the temp copy.
+        SubReg = SuperReg = CopyM0;
+        IsKill = true;
+      }
+
       BuildMI(*MBB, MI, DL,
               TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
               Spill.VGPR)
@@ -641,7 +664,13 @@ void SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
   unsigned SuperReg = MI->getOperand(0).getReg();
   bool SpillToSMEM = ST.hasScalarStores() && EnableSpillSGPRToSMEM;
 
-  assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
+  // m0 is not allowed as with readlane/writelane, so a temporary SGPR and
+  // extra copy is needed.
+  bool IsM0 = (SuperReg == AMDGPU::M0);
+  if (IsM0) {
+    assert(NumSubRegs == 1);
+    SuperReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
+  }
 
   int64_t FrOffset = FrameInfo.getObjectOffset(Index);
 
@@ -726,6 +755,11 @@ void SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
     }
   }
 
+  if (IsM0 && SuperReg != AMDGPU::M0) {
+    BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
+      .addReg(SuperReg);
+  }
+
   MI->eraseFromParent();
 }