From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 11 Feb 2019 16:16:09 +0000 (+0000)
Subject: [X86] Regenerate insertelement tests
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=e2953b930b569d9763ebdbc36d71fb5aef1f3303;p=llvm

[X86] Regenerate insertelement tests

Add common X86/X64 prefixes (and use X86 instead of X32)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353716 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/insertelement-shuffle.ll b/test/CodeGen/X86/insertelement-shuffle.ll
index 1756c2aa836..90934ed7945 100644
--- a/test/CodeGen/X86/insertelement-shuffle.ll
+++ b/test/CodeGen/X86/insertelement-shuffle.ll
@@ -1,41 +1,25 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown   -mattr=avx2    | FileCheck %s --check-prefix=X32_AVX256
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2    | FileCheck %s --check-prefix=X64_AVX256
-; RUN: llc < %s -mtriple=i686-unknown-unknown   -mattr=avx512f | FileCheck %s --check-prefix=X32_AVX512
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefix=X64_AVX512
+; RUN: llc < %s -mtriple=i686-unknown-unknown   -mattr=avx2    | FileCheck %s --check-prefixes=X86,X86_AVX256
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2    | FileCheck %s --check-prefixes=X64,X64_AVX256
+; RUN: llc < %s -mtriple=i686-unknown-unknown   -mattr=avx512f | FileCheck %s --check-prefixes=X86,X86_AVX512
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64,X64_AVX512
 
 define <8 x float> @insert_subvector_256(i16 %x0, i16 %x1, <8 x float> %v) nounwind {
-; X32_AVX256-LABEL: insert_subvector_256:
-; X32_AVX256:       # %bb.0:
-; X32_AVX256-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32_AVX256-NEXT:    vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
-; X32_AVX256-NEXT:    vpbroadcastd %xmm1, %xmm1
-; X32_AVX256-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
-; X32_AVX256-NEXT:    retl
+; X86-LABEL: insert_subvector_256:
+; X86:       # %bb.0:
+; X86-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X86-NEXT:    vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
+; X86-NEXT:    vpbroadcastd %xmm1, %xmm1
+; X86-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
+; X86-NEXT:    retl
 ;
-; X64_AVX256-LABEL: insert_subvector_256:
-; X64_AVX256:       # %bb.0:
-; X64_AVX256-NEXT:    vmovd %edi, %xmm1
-; X64_AVX256-NEXT:    vpinsrw $1, %esi, %xmm1, %xmm1
-; X64_AVX256-NEXT:    vpbroadcastd %xmm1, %xmm1
-; X64_AVX256-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
-; X64_AVX256-NEXT:    retq
-;
-; X32_AVX512-LABEL: insert_subvector_256:
-; X32_AVX512:       # %bb.0:
-; X32_AVX512-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32_AVX512-NEXT:    vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
-; X32_AVX512-NEXT:    vpbroadcastd %xmm1, %xmm1
-; X32_AVX512-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
-; X32_AVX512-NEXT:    retl
-;
-; X64_AVX512-LABEL: insert_subvector_256:
-; X64_AVX512:       # %bb.0:
-; X64_AVX512-NEXT:    vmovd %edi, %xmm1
-; X64_AVX512-NEXT:    vpinsrw $1, %esi, %xmm1, %xmm1
-; X64_AVX512-NEXT:    vpbroadcastd %xmm1, %xmm1
-; X64_AVX512-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
-; X64_AVX512-NEXT:    retq
+; X64-LABEL: insert_subvector_256:
+; X64:       # %bb.0:
+; X64-NEXT:    vmovd %edi, %xmm1
+; X64-NEXT:    vpinsrw $1, %esi, %xmm1, %xmm1
+; X64-NEXT:    vpbroadcastd %xmm1, %xmm1
+; X64-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
+; X64-NEXT:    retq
   %ins1 = insertelement <2 x i16> undef, i16 %x0, i32 0
   %ins2 = insertelement <2 x i16> %ins1, i16 %x1, i32 1
   %bc = bitcast <2 x i16> %ins2 to float
@@ -44,21 +28,21 @@ define <8 x float> @insert_subvector_256(i16 %x0, i16 %x1, <8 x float> %v) nounw
 }
 
 define <8 x i64> @insert_subvector_512(i32 %x0, i32 %x1, <8 x i64> %v) nounwind {
-; X32_AVX256-LABEL: insert_subvector_512:
-; X32_AVX256:       # %bb.0:
-; X32_AVX256-NEXT:    pushl %ebp
-; X32_AVX256-NEXT:    movl %esp, %ebp
-; X32_AVX256-NEXT:    andl $-8, %esp
-; X32_AVX256-NEXT:    subl $8, %esp
-; X32_AVX256-NEXT:    vmovsd {{.*#+}} xmm2 = mem[0],zero
-; X32_AVX256-NEXT:    vmovlps %xmm2, (%esp)
-; X32_AVX256-NEXT:    vextracti128 $1, %ymm0, %xmm2
-; X32_AVX256-NEXT:    vpinsrd $0, (%esp), %xmm2, %xmm2
-; X32_AVX256-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm2, %xmm2
-; X32_AVX256-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
-; X32_AVX256-NEXT:    movl %ebp, %esp
-; X32_AVX256-NEXT:    popl %ebp
-; X32_AVX256-NEXT:    retl
+; X86_AVX256-LABEL: insert_subvector_512:
+; X86_AVX256:       # %bb.0:
+; X86_AVX256-NEXT:    pushl %ebp
+; X86_AVX256-NEXT:    movl %esp, %ebp
+; X86_AVX256-NEXT:    andl $-8, %esp
+; X86_AVX256-NEXT:    subl $8, %esp
+; X86_AVX256-NEXT:    vmovsd {{.*#+}} xmm2 = mem[0],zero
+; X86_AVX256-NEXT:    vmovlps %xmm2, (%esp)
+; X86_AVX256-NEXT:    vextracti128 $1, %ymm0, %xmm2
+; X86_AVX256-NEXT:    vpinsrd $0, (%esp), %xmm2, %xmm2
+; X86_AVX256-NEXT:    vpinsrd $1, {{[0-9]+}}(%esp), %xmm2, %xmm2
+; X86_AVX256-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
+; X86_AVX256-NEXT:    movl %ebp, %esp
+; X86_AVX256-NEXT:    popl %ebp
+; X86_AVX256-NEXT:    retl
 ;
 ; X64_AVX256-LABEL: insert_subvector_512:
 ; X64_AVX256:       # %bb.0:
@@ -70,12 +54,12 @@ define <8 x i64> @insert_subvector_512(i32 %x0, i32 %x1, <8 x i64> %v) nounwind
 ; X64_AVX256-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
 ; X64_AVX256-NEXT:    retq
 ;
-; X32_AVX512-LABEL: insert_subvector_512:
-; X32_AVX512:       # %bb.0:
-; X32_AVX512-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero
-; X32_AVX512-NEXT:    vmovdqa64 {{.*#+}} zmm2 = [0,0,1,0,8,0,3,0,4,0,5,0,6,0,7,0]
-; X32_AVX512-NEXT:    vpermt2q %zmm1, %zmm2, %zmm0
-; X32_AVX512-NEXT:    retl
+; X86_AVX512-LABEL: insert_subvector_512:
+; X86_AVX512:       # %bb.0:
+; X86_AVX512-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero
+; X86_AVX512-NEXT:    vmovdqa64 {{.*#+}} zmm2 = [0,0,1,0,8,0,3,0,4,0,5,0,6,0,7,0]
+; X86_AVX512-NEXT:    vpermt2q %zmm1, %zmm2, %zmm0
+; X86_AVX512-NEXT:    retl
 ;
 ; X64_AVX512-LABEL: insert_subvector_512:
 ; X64_AVX512:       # %bb.0:
@@ -95,12 +79,12 @@ define <8 x i64> @insert_subvector_512(i32 %x0, i32 %x1, <8 x i64> %v) nounwind
 ; Special case: if we're inserting into an undef vector, we can optimize more.
 
 define <8 x i64> @insert_subvector_into_undef(i32 %x0, i32 %x1) nounwind {
-; X32_AVX256-LABEL: insert_subvector_into_undef:
-; X32_AVX256:       # %bb.0:
-; X32_AVX256-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X32_AVX256-NEXT:    vbroadcastsd %xmm0, %ymm0
-; X32_AVX256-NEXT:    vmovaps %ymm0, %ymm1
-; X32_AVX256-NEXT:    retl
+; X86_AVX256-LABEL: insert_subvector_into_undef:
+; X86_AVX256:       # %bb.0:
+; X86_AVX256-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X86_AVX256-NEXT:    vbroadcastsd %xmm0, %ymm0
+; X86_AVX256-NEXT:    vmovaps %ymm0, %ymm1
+; X86_AVX256-NEXT:    retl
 ;
 ; X64_AVX256-LABEL: insert_subvector_into_undef:
 ; X64_AVX256:       # %bb.0:
@@ -110,11 +94,11 @@ define <8 x i64> @insert_subvector_into_undef(i32 %x0, i32 %x1) nounwind {
 ; X64_AVX256-NEXT:    vmovdqa %ymm0, %ymm1
 ; X64_AVX256-NEXT:    retq
 ;
-; X32_AVX512-LABEL: insert_subvector_into_undef:
-; X32_AVX512:       # %bb.0:
-; X32_AVX512-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X32_AVX512-NEXT:    vbroadcastsd %xmm0, %zmm0
-; X32_AVX512-NEXT:    retl
+; X86_AVX512-LABEL: insert_subvector_into_undef:
+; X86_AVX512:       # %bb.0:
+; X86_AVX512-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X86_AVX512-NEXT:    vbroadcastsd %xmm0, %zmm0
+; X86_AVX512-NEXT:    retl
 ;
 ; X64_AVX512-LABEL: insert_subvector_into_undef:
 ; X64_AVX512:       # %bb.0: