From: Amaury Sechet Date: Mon, 27 Feb 2017 01:15:57 +0000 (+0000) Subject: Do full codegen for various tests. NFC X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=df8980ea704beb4ac480f5f25d2ab1a463393507;p=llvm Do full codegen for various tests. NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296305 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/ARM/neon_vabs.ll b/test/CodeGen/ARM/neon_vabs.ll index d32e7b78879..109d09582af 100644 --- a/test/CodeGen/ARM/neon_vabs.ll +++ b/test/CodeGen/ARM/neon_vabs.ll @@ -1,8 +1,15 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <4 x i32> @test1(<4 x i32> %a) nounwind { ; CHECK-LABEL: test1: -; CHECK: vabs.s32 q +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d17, r2, r3 +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vabs.s32 q8, q8 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: mov pc, lr %tmp1neg = sub <4 x i32> zeroinitializer, %a %b = icmp sgt <4 x i32> %a, %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg @@ -11,7 +18,13 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind { define <4 x i32> @test2(<4 x i32> %a) nounwind { ; CHECK-LABEL: test2: -; CHECK: vabs.s32 q +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d17, r2, r3 +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vabs.s32 q8, q8 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: mov pc, lr %tmp1neg = sub <4 x i32> zeroinitializer, %a %b = icmp sge <4 x i32> %a, zeroinitializer %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg @@ -20,7 +33,13 @@ define <4 x i32> @test2(<4 x i32> %a) nounwind { define <8 x i16> @test3(<8 x i16> %a) nounwind { ; CHECK-LABEL: test3: -; CHECK: vabs.s16 q +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d17, r2, r3 +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vabs.s16 q8, q8 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: mov pc, lr %tmp1neg = sub <8 x i16> zeroinitializer, %a %b = icmp sgt <8 x i16> %a, zeroinitializer %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg @@ -29,7 +48,13 @@ define <8 x i16> @test3(<8 x i16> %a) nounwind { define <16 x i8> @test4(<16 x i8> %a) nounwind { ; CHECK-LABEL: test4: -; CHECK: vabs.s8 q +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d17, r2, r3 +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vabs.s8 q8, q8 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: mov pc, lr %tmp1neg = sub <16 x i8> zeroinitializer, %a %b = icmp slt <16 x i8> %a, zeroinitializer %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a @@ -38,7 +63,13 @@ define <16 x i8> @test4(<16 x i8> %a) nounwind { define <4 x i32> @test5(<4 x i32> %a) nounwind { ; CHECK-LABEL: test5: -; CHECK: vabs.s32 q +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d17, r2, r3 +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vabs.s32 q8, q8 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: mov pc, lr %tmp1neg = sub <4 x i32> zeroinitializer, %a %b = icmp sle <4 x i32> %a, zeroinitializer %abs = select <4 x i1> %b, <4 x i32> %tmp1neg, <4 x i32> %a @@ -47,7 +78,11 @@ define <4 x i32> @test5(<4 x i32> %a) nounwind { define <2 x i32> @test6(<2 x i32> %a) nounwind { ; CHECK-LABEL: test6: -; CHECK: vabs.s32 d +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vabs.s32 d16, d16 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: mov pc, lr %tmp1neg = sub <2 x i32> zeroinitializer, %a %b = icmp sgt <2 x i32> %a, %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg @@ -56,7 +91,11 @@ define <2 x i32> @test6(<2 x i32> %a) nounwind { define <2 x i32> @test7(<2 x i32> %a) nounwind { ; CHECK-LABEL: test7: -; CHECK: vabs.s32 d +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vabs.s32 d16, d16 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: mov pc, lr %tmp1neg = sub <2 x i32> zeroinitializer, %a %b = icmp sge <2 x i32> %a, zeroinitializer %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg @@ -65,7 +104,11 @@ define <2 x i32> @test7(<2 x i32> %a) nounwind { define <4 x i16> @test8(<4 x i16> %a) nounwind { ; CHECK-LABEL: test8: -; CHECK: vabs.s16 d +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vabs.s16 d16, d16 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: mov pc, lr %tmp1neg = sub <4 x i16> zeroinitializer, %a %b = icmp sgt <4 x i16> %a, zeroinitializer %abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg @@ -74,7 +117,11 @@ define <4 x i16> @test8(<4 x i16> %a) nounwind { define <8 x i8> @test9(<8 x i8> %a) nounwind { ; CHECK-LABEL: test9: -; CHECK: vabs.s8 d +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vabs.s8 d16, d16 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: mov pc, lr %tmp1neg = sub <8 x i8> zeroinitializer, %a %b = icmp slt <8 x i8> %a, zeroinitializer %abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a @@ -83,7 +130,11 @@ define <8 x i8> @test9(<8 x i8> %a) nounwind { define <2 x i32> @test10(<2 x i32> %a) nounwind { ; CHECK-LABEL: test10: -; CHECK: vabs.s32 d +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d16, r0, r1 +; CHECK-NEXT: vabs.s32 d16, d16 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: mov pc, lr %tmp1neg = sub <2 x i32> zeroinitializer, %a %b = icmp sle <2 x i32> %a, zeroinitializer %abs = select <2 x i1> %b, <2 x i32> %tmp1neg, <2 x i32> %a @@ -95,7 +146,13 @@ define <2 x i32> @test10(<2 x i32> %a) nounwind { define <4 x i32> @test11(<4 x i16> %a, <4 x i16> %b) nounwind { ; CHECK-LABEL: test11: -; CHECK: vabdl.u16 q +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d16, r2, r3 +; CHECK-NEXT: vmov d17, r0, r1 +; CHECK-NEXT: vabdl.u16 q8, d17, d16 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: mov pc, lr %zext1 = zext <4 x i16> %a to <4 x i32> %zext2 = zext <4 x i16> %b to <4 x i32> %diff = sub <4 x i32> %zext1, %zext2 @@ -106,7 +163,13 @@ define <4 x i32> @test11(<4 x i16> %a, <4 x i16> %b) nounwind { } define <8 x i16> @test12(<8 x i8> %a, <8 x i8> %b) nounwind { ; CHECK-LABEL: test12: -; CHECK: vabdl.u8 q +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d16, r2, r3 +; CHECK-NEXT: vmov d17, r0, r1 +; CHECK-NEXT: vabdl.u8 q8, d17, d16 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: mov pc, lr %zext1 = zext <8 x i8> %a to <8 x i16> %zext2 = zext <8 x i8> %b to <8 x i16> %diff = sub <8 x i16> %zext1, %zext2 @@ -118,7 +181,13 @@ define <8 x i16> @test12(<8 x i8> %a, <8 x i8> %b) nounwind { define <2 x i64> @test13(<2 x i32> %a, <2 x i32> %b) nounwind { ; CHECK-LABEL: test13: -; CHECK: vabdl.u32 q +; CHECK: @ BB#0: +; CHECK-NEXT: vmov d16, r2, r3 +; CHECK-NEXT: vmov d17, r0, r1 +; CHECK-NEXT: vabdl.u32 q8, d17, d16 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: mov pc, lr %zext1 = zext <2 x i32> %a to <2 x i64> %zext2 = zext <2 x i32> %b to <2 x i64> %diff = sub <2 x i64> %zext1, %zext2 diff --git a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll index 264967157d7..56f4a4173ef 100644 --- a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll +++ b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll @@ -1,17 +1,33 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin | grep extsw | count 2 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s @lens = external global i8* ; [#uses=1] @vals = external global i32* ; [#uses=1] define i32 @test(i32 %i) { - %tmp = load i8*, i8** @lens ; [#uses=1] - %tmp1 = getelementptr i8, i8* %tmp, i32 %i ; [#uses=1] - %tmp.upgrd.1 = load i8, i8* %tmp1 ; [#uses=1] - %tmp2 = zext i8 %tmp.upgrd.1 to i32 ; [#uses=1] - %tmp3 = load i32*, i32** @vals ; [#uses=1] - %tmp5 = sub i32 1, %tmp2 ; [#uses=1] - %tmp6 = getelementptr i32, i32* %tmp3, i32 %tmp5 ; [#uses=1] - %tmp7 = load i32, i32* %tmp6 ; [#uses=1] - ret i32 %tmp7 +; CHECK-LABEL: test: +; CHECK: # BB#0: +; CHECK-NEXT: addis 4, 2, .LC0@toc@ha +; CHECK-NEXT: extsw 3, 3 +; CHECK-NEXT: addis 5, 2, .LC1@toc@ha +; CHECK-NEXT: ld 4, .LC0@toc@l(4) +; CHECK-NEXT: ld 4, 0(4) +; CHECK-NEXT: lbzx 3, 4, 3 +; CHECK-NEXT: ld 4, .LC1@toc@l(5) +; CHECK-NEXT: subfic 3, 3, 1 +; CHECK-NEXT: extsw 3, 3 +; CHECK-NEXT: ld 4, 0(4) +; CHECK-NEXT: sldi 3, 3, 2 +; CHECK-NEXT: lwzx 3, 4, 3 +; CHECK-NEXT: blr + %tmp = load i8*, i8** @lens ; [#uses=1] + %tmp1 = getelementptr i8, i8* %tmp, i32 %i ; [#uses=1] + %tmp.upgrd.1 = load i8, i8* %tmp1 ; [#uses=1] + %tmp2 = zext i8 %tmp.upgrd.1 to i32 ; [#uses=1] + %tmp3 = load i32*, i32** @vals ; [#uses=1] + %tmp5 = sub i32 1, %tmp2 ; [#uses=1] + %tmp6 = getelementptr i32, i32* %tmp3, i32 %tmp5 ; [#uses=1] + %tmp7 = load i32, i32* %tmp6 ; [#uses=1] + ret i32 %tmp7 } diff --git a/test/CodeGen/PowerPC/setcc-to-sub.ll b/test/CodeGen/PowerPC/setcc-to-sub.ll index 335bb403cd7..752ebe0c9d8 100644 --- a/test/CodeGen/PowerPC/setcc-to-sub.ll +++ b/test/CodeGen/PowerPC/setcc-to-sub.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 < %s | FileCheck %s @@ -6,6 +7,15 @@ ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test1(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { +; CHECK-LABEL: test1: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: lwz 3, 0(3) +; CHECK-NEXT: lwz 4, 0(4) +; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 +; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 +; CHECK-NEXT: sub 3, 3, 4 +; CHECK-NEXT: rldicl 3, 3, 1, 63 +; CHECK-NEXT: blr entry: %arrayidx.i6 = bitcast %class.PB2* %s_a to i32* %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1 @@ -15,18 +25,20 @@ entry: %and.i4 = and i32 %1, 8 %cmp.i5 = icmp ult i32 %and.i, %and.i4 ret i1 %cmp.i5 - -; CHECK-LABEL: @test1 -; CHECK: rlwinm [[REG1:[0-9]*]] -; CHECK-NEXT: rlwinm [[REG2:[0-9]*]] -; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG1]], [[REG2]] -; CHECK-NEXT: rldicl 3, [[REG3]] -; CHECK: blr - } ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test2(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { +; CHECK-LABEL: test2: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: lwz 3, 0(3) +; CHECK-NEXT: lwz 4, 0(4) +; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 +; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 +; CHECK-NEXT: sub 3, 4, 3 +; CHECK-NEXT: rldicl 3, 3, 1, 63 +; CHECK-NEXT: xori 3, 3, 1 +; CHECK-NEXT: blr entry: %arrayidx.i6 = bitcast %class.PB2* %s_a to i32* %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1 @@ -36,19 +48,19 @@ entry: %and.i4 = and i32 %1, 8 %cmp.i5 = icmp ule i32 %and.i, %and.i4 ret i1 %cmp.i5 - -; CHECK-LABEL: @test2 -; CHECK: rlwinm [[REG1:[0-9]*]] -; CHECK-NEXT: rlwinm [[REG2:[0-9]*]] -; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG2]], [[REG1]] -; CHECK-NEXT: rldicl [[REG4:[0-9]*]], [[REG3]] -; CHECK-NEXT: xori 3, [[REG4]], 1 -; CHECK: blr - } ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test3(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { +; CHECK-LABEL: test3: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: lwz 3, 0(3) +; CHECK-NEXT: lwz 4, 0(4) +; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 +; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 +; CHECK-NEXT: sub 3, 4, 3 +; CHECK-NEXT: rldicl 3, 3, 1, 63 +; CHECK-NEXT: blr entry: %arrayidx.i6 = bitcast %class.PB2* %s_a to i32* %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1 @@ -58,18 +70,20 @@ entry: %and.i4 = and i32 %1, 8 %cmp.i5 = icmp ugt i32 %and.i, %and.i4 ret i1 %cmp.i5 - -; CHECK-LABEL: @test3 -; CHECK: rlwinm [[REG1:[0-9]*]] -; CHECK-NEXT: rlwinm [[REG2:[0-9]*]] -; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG2]], [[REG1]] -; CHECK-NEXT: rldicl 3, [[REG3]] -; CHECK: blr - } ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test4(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { +; CHECK-LABEL: test4: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: lwz 3, 0(3) +; CHECK-NEXT: lwz 4, 0(4) +; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 +; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 +; CHECK-NEXT: sub 3, 3, 4 +; CHECK-NEXT: rldicl 3, 3, 1, 63 +; CHECK-NEXT: xori 3, 3, 1 +; CHECK-NEXT: blr entry: %arrayidx.i6 = bitcast %class.PB2* %s_a to i32* %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1 @@ -79,15 +93,6 @@ entry: %and.i4 = and i32 %1, 8 %cmp.i5 = icmp uge i32 %and.i, %and.i4 ret i1 %cmp.i5 - -; CHECK-LABEL: @test4 -; CHECK: rlwinm [[REG1:[0-9]*]] -; CHECK-NEXT: rlwinm [[REG2:[0-9]*]] -; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG1]], [[REG2]] -; CHECK-NEXT: rldicl [[REG4:[0-9]*]], [[REG3]] -; CHECK-NEXT: xori 3, [[REG4]], 1 -; CHECK: blr - } !1 = !{!2, !2, i64 0}