From: Ivan Grokhotkov <ivan@espressif.com>
Date: Thu, 29 Nov 2018 07:15:21 +0000 (+0800)
Subject: soc/rtc_clk: don’t clear DPORT_CPUPERIOD_SEL when switching to XTAL
X-Git-Tag: v3.3-beta2~14^2~2
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=dda0208614dc418068779780b5eb1bad57579718;p=esp-idf

soc/rtc_clk: don’t clear DPORT_CPUPERIOD_SEL when switching to XTAL

This is not necessary since RTC_CNTL_SOC_CLK_SEL is set before this.
---

diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c
index 3156517b92..b88f59bdc6 100644
--- a/components/soc/esp32/rtc_clk.c
+++ b/components/soc/esp32/rtc_clk.c
@@ -398,7 +398,6 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div)
     REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, freq * MHZ / REF_CLK_FREQ - 1);
     /* switch clock source */
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
-    DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); /* clear DPORT_CPUPERIOD_SEL */
     rtc_clk_apb_freq_update(freq * MHZ);
     /* lower the voltage */
     if (freq <= 2) {
@@ -414,7 +413,6 @@ static void rtc_clk_cpu_freq_to_8m()
     REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
     REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M);
-    DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL
     rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
 }