From: Tim Northover <tnorthover@apple.com>
Date: Fri, 17 Feb 2017 18:50:15 +0000 (+0000)
Subject: GlobalISel: verify that generic loads & stores have a mem operand.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=dc88467192842cd17ca8931347a8a959b259ad6a;p=llvm

GlobalISel: verify that generic loads & stores have a mem operand.

The mem operand is used by GlobalISel to convey atomic constraints so dropping
it is invalid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295476 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp
index 74709dc0888..15694cb481f 100644
--- a/lib/CodeGen/MachineVerifier.cpp
+++ b/lib/CodeGen/MachineVerifier.cpp
@@ -908,6 +908,14 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     }
   }
 
+  // Generic loads and stores must have a single MachineMemOperand
+  // describing that access.
+  if ((MI->getOpcode() == TargetOpcode::G_LOAD ||
+       MI->getOpcode() == TargetOpcode::G_STORE) &&
+      !MI->hasOneMemOperand())
+    report("Generic instruction accessing memory must have one mem operand",
+           MI);
+
   StringRef ErrorInfo;
   if (!TII->verifyInstruction(*MI, ErrorInfo))
     report(ErrorInfo.data(), MI);
diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
index 12162eb54a8..14ee40c941b 100644
--- a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -622,7 +622,7 @@ body: |
     ; CHECK:      %0(p0) = COPY %x0
     ; CHECK:      %1(s32) = G_LOAD %0
     %0(p0) = COPY %x0
-    %1(s32) = G_LOAD %0
+    %1(s32) = G_LOAD %0 :: (load 4)
 ...
 
 ---
@@ -643,7 +643,7 @@ body: |
     ; CHECK:      G_STORE %1(s32), %0(p0)
     %0(p0) = COPY %x0
     %1(s32) = COPY %w1
-    G_STORE %1, %0
+    G_STORE %1, %0 :: (store 4)
 ...
 
 ---
diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index 77dcccde3f6..25c5efd6a61 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -320,13 +320,13 @@ body:             |
     %0(p0) = G_FRAME_INDEX %fixed-stack.2
     ; CHECK: [[FI32VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI32]], 0, 14, _, _
 
-    %1(s32) = G_LOAD %0(p0)
+    %1(s32) = G_LOAD %0(p0) :: (load 4)
     ; CHECK: {{%[0-9]+}} = LDRi12 [[FI32VREG]], 0, 14, _
 
     %2(p0) = G_FRAME_INDEX %fixed-stack.0
     ; CHECK: [[FI1VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI1]], 0, 14, _, _
 
-    %3(s1) = G_LOAD %2(p0)
+    %3(s1) = G_LOAD %2(p0) :: (load 1)
     ; CHECK: {{%[0-9]+}} = LDRBi12 [[FI1VREG]], 0, 14, _
 
     BX_RET 14, _
@@ -350,7 +350,7 @@ body:             |
 
     %0(p0) = COPY %r0
 
-    %1(s32) = G_LOAD %0(p0)
+    %1(s32) = G_LOAD %0(p0) :: (load 4)
     ; CHECK: %[[V]] = VLDRS %[[P]], 0, 14, _
 
     %s0 = COPY %1
@@ -377,7 +377,7 @@ body:             |
 
     %0(p0) = COPY %r0
 
-    %1(s64) = G_LOAD %0(p0)
+    %1(s64) = G_LOAD %0(p0) :: (load 8)
     ; CHECK: %[[V]] = VLDRD %[[P]], 0, 14, _
 
     %d0 = COPY %1
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index 8ed4870ba89..4943a7305fb 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -157,9 +157,9 @@ body:             |
 
     ; This is legal, so we should find it unchanged in the output
     ; CHECK: [[FIVREG:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
-    ; CHECK: {{%[0-9]+}}(s32) = G_LOAD [[FIVREG]](p0)
+    ; CHECK: {{%[0-9]+}}(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
     %0(p0) = G_FRAME_INDEX %fixed-stack.2
-    %1(s32) = G_LOAD %0(p0)
+    %1(s32) = G_LOAD %0(p0) :: (load 4)
     BX_RET 14, _
 ...
 ---
@@ -190,12 +190,12 @@ body:             |
     ; CHECK-DAG: {{%[0-9]+}}(s1) = G_LOAD %0
     ; CHECK-DAG: {{%[0-9]+}}(p0) = G_LOAD %0
     %0(p0) = COPY %r0
-    %1(s32) = G_LOAD %0(p0)
-    %2(s16) = G_LOAD %0(p0)
-    %3(s8)  = G_LOAD %0(p0)
-    %4(s1)  = G_LOAD %0(p0)
-    %5(p0)  = G_LOAD %0(p0)
-    %6(s64) = G_LOAD %0(p0)
+    %1(s32) = G_LOAD %0(p0) :: (load 4)
+    %2(s16) = G_LOAD %0(p0) :: (load 2)
+    %3(s8)  = G_LOAD %0(p0) :: (load 1)
+    %4(s1)  = G_LOAD %0(p0) :: (load 1)
+    %5(p0)  = G_LOAD %0(p0) :: (load 4)
+    %6(s64) = G_LOAD %0(p0) :: (load 8)
     BX_RET 14, _
 ...
 ---
diff --git a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
index 4ed778a5939..e54ca39b3ae 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -145,12 +145,12 @@ body:             |
   bb.0:
     liveins: %r0
     %0(p0) = COPY %r0
-    %6(s64) = G_LOAD %0
-    %1(s32) = G_LOAD %0
-    %2(s16) = G_LOAD %0
-    %3(s8)  = G_LOAD %0
-    %4(s1)  = G_LOAD %0
-    %5(p0)  = G_LOAD %0
+    %6(s64) = G_LOAD %0 :: (load 8)
+    %1(s32) = G_LOAD %0 :: (load 4)
+    %2(s16) = G_LOAD %0 :: (load 2)
+    %3(s8)  = G_LOAD %0 :: (load 1)
+    %4(s1)  = G_LOAD %0 :: (load 1)
+    %5(p0)  = G_LOAD %0 :: (load 8)
     BX_RET 14, _, implicit %r0
 
 ...