From: Roman Lebedev <lebedev.ri@gmail.com>
Date: Tue, 4 Jun 2019 17:05:06 +0000 (+0000)
Subject: [NFC][Codegen][AMDGPU] Autogenerate commute-shifts.ll test
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=dc24cf3e99d381a36d9200bed5d7d25002753c23;p=llvm

[NFC][Codegen][AMDGPU] Autogenerate commute-shifts.ll test

Being affected by upcoming patch

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362528 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/AMDGPU/commute-shifts.ll b/test/CodeGen/AMDGPU/commute-shifts.ll
index 415a3156699..81ca354574d 100644
--- a/test/CodeGen/AMDGPU/commute-shifts.ll
+++ b/test/CodeGen/AMDGPU/commute-shifts.ll
@@ -1,10 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
 
-; GCN-LABEL: {{^}}main:
-; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
-; VI: v_lshlrev_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 1
 define amdgpu_ps float @main(float %arg0, float %arg1) #0 {
+; SI-LABEL: main:
+; SI:       ; %bb.0: ; %bb
+; SI-NEXT:    v_cvt_i32_f32_e32 v0, v0
+; SI-NEXT:    s_mov_b32 s0, 0
+; SI-NEXT:    s_mov_b32 s1, s0
+; SI-NEXT:    s_mov_b32 s2, s0
+; SI-NEXT:    s_mov_b32 s3, s0
+; SI-NEXT:    s_mov_b32 s4, s0
+; SI-NEXT:    s_mov_b32 s5, s0
+; SI-NEXT:    s_mov_b32 s6, s0
+; SI-NEXT:    s_mov_b32 s7, s0
+; SI-NEXT:    image_load v2, v0, s[0:7] dmask:0x1 unorm
+; SI-NEXT:    v_and_b32_e32 v0, 7, v0
+; SI-NEXT:    v_lshl_b32_e32 v0, 1, v0
+; SI-NEXT:    s_waitcnt vmcnt(0)
+; SI-NEXT:    v_and_b32_e32 v0, v2, v0
+; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-NEXT:    v_cvt_pkrtz_f16_f32_e32 v0, s0, v0
+; SI-NEXT:    ; return to shader part epilog
+;
+; VI-LABEL: main:
+; VI:       ; %bb.0: ; %bb
+; VI-NEXT:    v_cvt_i32_f32_e32 v0, v0
+; VI-NEXT:    s_mov_b32 s0, 0
+; VI-NEXT:    s_mov_b32 s1, s0
+; VI-NEXT:    s_mov_b32 s2, s0
+; VI-NEXT:    s_mov_b32 s3, s0
+; VI-NEXT:    s_mov_b32 s4, s0
+; VI-NEXT:    s_mov_b32 s5, s0
+; VI-NEXT:    s_mov_b32 s6, s0
+; VI-NEXT:    s_mov_b32 s7, s0
+; VI-NEXT:    image_load v2, v0, s[0:7] dmask:0x1 unorm
+; VI-NEXT:    v_and_b32_e32 v0, 7, v0
+; VI-NEXT:    v_lshlrev_b32_e64 v0, v0, 1
+; VI-NEXT:    s_waitcnt vmcnt(0)
+; VI-NEXT:    v_and_b32_e32 v0, v2, v0
+; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; VI-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-NEXT:    v_cvt_pkrtz_f16_f32 v0, s0, v0
+; VI-NEXT:    ; return to shader part epilog
 bb:
   %tmp = fptosi float %arg0 to i32
   %tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 undef, <8 x i32> undef, i32 0, i32 0)