From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 11 Dec 2017 15:53:12 +0000 (+0000)
Subject: [X86] Add CLZERO schedule test
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=db0d1d38bad3004c31229c0494f57c27c3818feb;p=llvm

[X86] Add CLZERO schedule test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320382 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/clzero-schedule.ll b/test/CodeGen/X86/clzero-schedule.ll
new file mode 100644
index 00000000000..3a1c1b2cdc7
--- /dev/null
+++ b/test/CodeGen/X86/clzero-schedule.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+clzero | FileCheck %s --check-prefix=GENERIC
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=ZNVER1
+
+define void @test_clzero(i8* %p) {
+; GENERIC-LABEL: test_clzero:
+; GENERIC:       # %bb.0:
+; GENERIC-NEXT:    leaq (%rdi), %rax # sched: [1:0.50]
+; GENERIC-NEXT:    clzero # sched: [100:0.33]
+; GENERIC-NEXT:    retq # sched: [1:1.00]
+;
+; ZNVER1-LABEL: test_clzero:
+; ZNVER1:       # %bb.0:
+; ZNVER1-NEXT:    leaq (%rdi), %rax # sched: [1:0.25]
+; ZNVER1-NEXT:    clzero # sched: [100:?]
+; ZNVER1-NEXT:    retq # sched: [1:0.50]
+  tail call void @llvm.x86.clzero(i8* %p)
+  ret void
+}
+declare void @llvm.x86.clzero(i8*)