From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Wed, 5 Jun 2019 16:14:14 +0000 (+0000)
Subject: [X86][AVX] Generalize split256BitStore to splitVectorStore. NFCI.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=dadb4c59097d64175824877df3606bc3dd59f2de;p=llvm

[X86][AVX] Generalize split256BitStore to splitVectorStore. NFCI.

Enables us to use this to split 512-bit vectors in future patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362617 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index a6aa2b77990..63f0c8b4004 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -21016,10 +21016,12 @@ static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget &Subtarget,
   return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
 }
 
-/// Change a 256-bit vector store into a pair of 128-bit vector stores.
-static SDValue split256BitStore(StoreSDNode *Store, SelectionDAG &DAG) {
+/// Change a vector store into a pair of half-size vector stores.
+static SDValue splitVectorStore(StoreSDNode *Store, SelectionDAG &DAG) {
   SDValue StoredVal = Store->getValue();
-  assert(StoredVal.getValueType().is256BitVector() && "Expecting 256-bit op");
+  assert((StoredVal.getValueType().is256BitVector() ||
+          StoredVal.getValueType().is512BitVector()) &&
+         "Expecting 256/512-bit op");
 
   // Splitting volatile memory ops is not allowed unless the operation was not
   // legal to begin with. We are assuming the input op is legal (this transform
@@ -21029,19 +21031,22 @@ static SDValue split256BitStore(StoreSDNode *Store, SelectionDAG &DAG) {
 
   MVT StoreVT = StoredVal.getSimpleValueType();
   unsigned NumElems = StoreVT.getVectorNumElements();
+  unsigned HalfSize = StoredVal.getValueSizeInBits() / 2;
+  unsigned HalfAlign = (128 == HalfSize ? 16 : 32);
+
   SDLoc DL(Store);
-  SDValue Value0 = extract128BitVector(StoredVal, 0, DAG, DL);
-  SDValue Value1 = extract128BitVector(StoredVal, NumElems / 2, DAG, DL);
+  SDValue Value0 = extractSubVector(StoredVal, 0, DAG, DL, HalfSize);
+  SDValue Value1 = extractSubVector(StoredVal, NumElems / 2, DAG, DL, HalfSize);
   SDValue Ptr0 = Store->getBasePtr();
-  SDValue Ptr1 = DAG.getMemBasePlusOffset(Ptr0, 16, DL);
+  SDValue Ptr1 = DAG.getMemBasePlusOffset(Ptr0, HalfAlign, DL);
   unsigned Alignment = Store->getAlignment();
   SDValue Ch0 =
       DAG.getStore(Store->getChain(), DL, Value0, Ptr0, Store->getPointerInfo(),
                    Alignment, Store->getMemOperand()->getFlags());
-  SDValue Ch1 =
-      DAG.getStore(Store->getChain(), DL, Value1, Ptr1,
-                   Store->getPointerInfo().getWithOffset(16),
-                   MinAlign(Alignment, 16), Store->getMemOperand()->getFlags());
+  SDValue Ch1 = DAG.getStore(Store->getChain(), DL, Value1, Ptr1,
+                             Store->getPointerInfo().getWithOffset(HalfAlign),
+                             MinAlign(Alignment, HalfAlign),
+                             Store->getMemOperand()->getFlags());
   return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Ch0, Ch1);
 }
 
@@ -21082,7 +21087,7 @@ static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget,
   if (StoreVT.is256BitVector()) {
     if (StoredVal.getOpcode() != ISD::CONCAT_VECTORS || !StoredVal.hasOneUse())
       return SDValue();
-    return split256BitStore(St, DAG);
+    return splitVectorStore(St, DAG);
   }
 
   assert(StoreVT.isVector() && StoreVT.getSizeInBits() == 64 &&
@@ -39464,7 +39469,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
     if (NumElems < 2)
       return SDValue();
 
-    return split256BitStore(St, DAG);
+    return splitVectorStore(St, DAG);
   }
 
   // Optimize trunc store (of multiple scalars) to shuffle and store.