From: Sanjay Patel Date: Thu, 3 Oct 2019 14:34:28 +0000 (+0000) Subject: [UpdateTestChecks] add basic support for parsing msp430 asm X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=da186b07ad70e5878b904b83263ee8f52e13f90e;p=llvm [UpdateTestChecks] add basic support for parsing msp430 asm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373605 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/utils/UpdateTestChecks/asm.py b/utils/UpdateTestChecks/asm.py index 1eb354d8a46..81556d65802 100644 --- a/utils/UpdateTestChecks/asm.py +++ b/utils/UpdateTestChecks/asm.py @@ -58,6 +58,12 @@ ASM_FUNCTION_MIPS_RE = re.compile( # .Lfunc_end0: (mips64 - NewABI) flags=(re.M | re.S)) +ASM_FUNCTION_MSP430_RE = re.compile( + r'^_?(?P[^:]+):[ \t]*;+[ \t]*@(?P=func)\n[^:]*?' + r'(?P.*?)\n' + r'(\$|\.L)func_end[0-9]+:\n', # $func_end0: + flags=(re.M | re.S)) + ASM_FUNCTION_PPC_RE = re.compile( r'^_?(?P[^:]+):[ \t]*#+[ \t]*@(?P=func)\n' r'.*?' @@ -231,6 +237,16 @@ def scrub_asm_mips(asm, args): asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm) return asm +def scrub_asm_msp430(asm, args): + # Scrub runs of whitespace out of the assembly, but leave the leading + # whitespace in place. + asm = common.SCRUB_WHITESPACE_RE.sub(r' ', asm) + # Expand the tabs used for indentation. + asm = string.expandtabs(asm, 2) + # Strip trailing whitespace. + asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm) + return asm + def scrub_asm_riscv(asm, args): # Scrub runs of whitespace out of the assembly, but leave the leading # whitespace in place. @@ -315,6 +331,7 @@ def build_function_body_dictionary_for_triple(args, raw_tool_output, triple, pre 'thumbv5-macho': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_MACHO_RE), 'thumbv7-apple-ios' : (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_IOS_RE), 'mips': (scrub_asm_mips, ASM_FUNCTION_MIPS_RE), + 'msp430': (scrub_asm_msp430, ASM_FUNCTION_MSP430_RE), 'ppc32': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE), 'powerpc': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE), 'riscv32': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),