From: Ayman Musa <ayman.musa@intel.com>
Date: Sun, 3 Sep 2017 09:09:16 +0000 (+0000)
Subject: [X86] Fix crash on assert of non-simple type after type-legalization
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=d9cee299c04c70bf2373bd73c1b7624970540d5a;p=llvm

[X86] Fix crash on assert of non-simple type after type-legalization

The function combineShuffleToVectorExtend in DAGCombine might generate an illegal typed node after "legalize types" phase, causing assertion on non-simple type to fail afterwards.

Adding a type check in case the combine is running after the type legalize pass.

Differential Revision: https://reviews.llvm.org/D37330

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312438 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6dbfced44d1..ae923e8ac07 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -15492,7 +15492,8 @@ static SDValue combineShuffleOfScalars(ShuffleVectorSDNode *SVN,
 static SDValue combineShuffleToVectorExtend(ShuffleVectorSDNode *SVN,
                                             SelectionDAG &DAG,
                                             const TargetLowering &TLI,
-                                            bool LegalOperations) {
+                                            bool LegalOperations,
+                                            bool LegalTypes) {
   EVT VT = SVN->getValueType(0);
   bool IsBigEndian = DAG.getDataLayout().isBigEndian();
 
@@ -15525,9 +15526,10 @@ static SDValue combineShuffleToVectorExtend(ShuffleVectorSDNode *SVN,
 
     EVT OutSVT = EVT::getIntegerVT(*DAG.getContext(), EltSizeInBits * Scale);
     EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale);
-    if (!LegalOperations ||
-        TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT))
-      return DAG.getBitcast(VT,
+    if (!LegalTypes || TLI.isTypeLegal(OutVT))
+      if (!LegalOperations ||
+          TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT))
+        return DAG.getBitcast(VT,
                             DAG.getAnyExtendVectorInReg(N0, SDLoc(SVN), OutVT));
   }
 
@@ -15758,7 +15760,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
     return S;
 
   // Match shuffles that can be converted to any_vector_extend_in_reg.
-  if (SDValue V = combineShuffleToVectorExtend(SVN, DAG, TLI, LegalOperations))
+  if (SDValue V = combineShuffleToVectorExtend(SVN, DAG, TLI, LegalOperations, LegalTypes))
     return V;
 
   // Combine "truncate_vector_in_reg" style shuffles.
diff --git a/test/CodeGen/X86/pr34397.ll b/test/CodeGen/X86/pr34397.ll
new file mode 100644
index 00000000000..778968f6d0c
--- /dev/null
+++ b/test/CodeGen/X86/pr34397.ll
@@ -0,0 +1,22 @@
+target triple = "x86_64-unknown-linux-gnu"
+
+define internal fastcc <32 x i64> @test(<32 x i64> %s.0.6, <32 x i64> %s.0.7) {
+entry:
+  %s.1.6 = shufflevector <32 x i64> %s.0.6, <32 x i64> %s.0.7, <32 x i32> <i32 13, i32 12, i32 51, i32 20, i32 19, i32 14, i32 41, i32 0, i32 21, i32 11, i32 32, i32 32, i32 11, i32 7, i32 19, i32 11, i32 53, i32 11, i32 34, i32 27, i32 35, i32 5, i32 52, i32 29, i32 5, i32 24, i32 3, i32 29, i32 57, i32 0, i32 47, i32 50>
+  %s.2.5 = shufflevector <32 x i64> undef, <32 x i64> %s.1.6, <32 x i32> <i32 7, i32 56, i32 38, i32 60, i32 44, i32 38, i32 26, i32 23, i32 45, i32 52, i32 60, i32 60, i32 54, i32 25, i32 25, i32 51, i32 45, i32 62, i32 20, i32 54, i32 6, i32 30, i32 6, i32 1, i32 47, i32 47, i32 49, i32 19, i32 16, i32 40, i32 24, i32 59>
+  %s.3.4 = shufflevector <32 x i64> undef, <32 x i64> %s.2.5, <32 x i32> <i32 7, i32 38, i32 37, i32 24, i32 41, i32 43, i32 38, i32 43, i32 29, i32 47, i32 11, i32 5, i32 40, i32 61, i32 10, i32 2, i32 37, i32 51, i32 46, i32 53, i32 51, i32 25, i32 20, i32 20, i32 27, i32 60, i32 20, i32 13, i32 45, i32 58, i32 35, i32 28>
+  %s.4.4 = shufflevector <32 x i64> %s.3.4, <32 x i64> undef, <32 x i32> <i32 35, i32 17, i32 38, i32 57, i32 61, i32 9, i32 22, i32 13, i32 62, i32 49, i32 18, i32 21, i32 58, i32 30, i32 23, i32 15, i32 27, i32 11, i32 22, i32 29, i32 62, i32 61, i32 63, i32 45, i32 41, i32 57, i32 59, i32 57, i32 15, i32 58, i32 62, i32 56>
+  %s.5.4 = shufflevector <32 x i64> %s.4.4, <32 x i64> undef, <32 x i32> <i32 33, i32 45, i32 18, i32 59, i32 17, i32 33, i32 35, i32 5, i32 43, i32 30, i32 20, i32 47, i32 22, i32 48, i32 55, i32 59, i32 13, i32 15, i32 2, i32 52, i32 26, i32 57, i32 25, i32 17, i32 17, i32 17, i32 24, i32 46, i32 31, i32 49, i32 47, i32 22>
+  %s.6.3 = shufflevector <32 x i64> undef, <32 x i64> %s.5.4, <32 x i32> <i32 48, i32 15, i32 24, i32 53, i32 57, i32 40, i32 24, i32 33, i32 47, i32 53, i32 44, i32 62, i32 6, i32 15, i32 47, i32 55, i32 0, i32 59, i32 36, i32 63, i32 36, i32 50, i32 53, i32 29, i32 24, i32 49, i32 8, i32 42, i32 17, i32 58, i32 47, i32 38>
+  %s.7.2 = shufflevector <32 x i64> undef, <32 x i64> %s.6.3, <32 x i32> <i32 55, i32 0, i32 3, i32 60, i32 17, i32 20, i32 5, i32 8, i32 61, i32 44, i32 1, i32 50, i32 11, i32 17, i32 48, i32 48, i32 38, i32 41, i32 46, i32 55, i32 15, i32 54, i32 32, i32 60, i32 35, i32 40, i32 27, i32 53, i32 29, i32 44, i32 45, i32 16>
+  %s.8.2 = shufflevector <32 x i64> %s.7.2, <32 x i64> zeroinitializer, <32 x i32> <i32 26, i32 46, i32 1, i32 47, i32 29, i32 1, i32 22, i32 8, i32 55, i32 1, i32 41, i32 25, i32 63, i32 19, i32 42, i32 2, i32 17, i32 45, i32 15, i32 55, i32 52, i32 31, i32 22, i32 9, i32 34, i32 34, i32 36, i32 11, i32 48, i32 34, i32 38, i32 42>
+  %s.9.2 = shufflevector <32 x i64> %s.8.2, <32 x i64> undef, <32 x i32> <i32 19, i32 48, i32 5, i32 38, i32 38, i32 4, i32 41, i32 26, i32 7, i32 34, i32 15, i32 9, i32 22, i32 30, i32 9, i32 59, i32 12, i32 55, i32 30, i32 48, i32 34, i32 15, i32 33, i32 61, i32 63, i32 36, i32 28, i32 28, i32 22, i32 62, i32 50, i32 42>
+  %s.10.1 = shufflevector <32 x i64> undef, <32 x i64> %s.9.2, <32 x i32> <i32 38, i32 5, i32 44, i32 3, i32 4, i32 50, i32 42, i32 43, i32 9, i32 27, i32 14, i32 45, i32 5, i32 63, i32 6, i32 44, i32 49, i32 59, i32 35, i32 45, i32 30, i32 9, i32 54, i32 13, i32 56, i32 12, i32 54, i32 3, i32 21, i32 60, i32 49, i32 53>
+  %s.11.1 = shufflevector <32 x i64> %s.10.1, <32 x i64> undef, <32 x i32> <i32 50, i32 17, i32 3, i32 40, i32 26, i32 29, i32 54, i32 46, i32 2, i32 31, i32 7, i32 18, i32 51, i32 63, i32 42, i32 55, i32 15, i32 13, i32 52, i32 20, i32 50, i32 51, i32 22, i32 2, i32 49, i32 29, i32 61, i32 20, i32 2, i32 49, i32 46, i32 22>
+  %s.12.1 = shufflevector <32 x i64> %s.11.1, <32 x i64> undef, <32 x i32> <i32 26, i32 58, i32 25, i32 54, i32 53, i32 9, i32 17, i32 13, i32 18, i32 48, i32 49, i32 63, i32 19, i32 46, i32 22, i32 28, i32 23, i32 58, i32 58, i32 13, i32 22, i32 1, i32 11, i32 41, i32 19, i32 28, i32 20, i32 37, i32 12, i32 25, i32 26, i32 48>
+  %s.13.1 = shufflevector <32 x i64> %s.12.1, <32 x i64> undef, <32 x i32> <i32 15, i32 26, i32 60, i32 19, i32 16, i32 23, i32 61, i32 31, i32 45, i32 32, i32 17, i32 19, i32 35, i32 6, i32 3, i32 1, i32 19, i32 35, i32 46, i32 14, i32 36, i32 50, i32 38, i32 25, i32 21, i32 38, i32 24, i32 24, i32 5, i32 55, i32 8, i32 33>
+  %s.14.0 = shufflevector <32 x i64> undef, <32 x i64> %s.13.1, <32 x i32> <i32 6, i32 9, i32 23, i32 55, i32 45, i32 0, i32 7, i32 28, i32 6, i32 10, i32 49, i32 63, i32 50, i32 26, i32 9, i32 41, i32 41, i32 30, i32 20, i32 55, i32 17, i32 53, i32 13, i32 10, i32 32, i32 36, i32 24, i32 4, i32 36, i32 21, i32 59, i32 49>
+  %s.15.0 = shufflevector <32 x i64> %s.14.0, <32 x i64> undef, <32 x i32> <i32 8, i32 22, i32 30, i32 45, i32 10, i32 60, i32 27, i32 14, i32 21, i32 26, i32 27, i32 28, i32 5, i32 47, i32 12, i32 47, i32 26, i32 18, i32 27, i32 47, i32 47, i32 20, i32 27, i32 18, i32 60, i32 36, i32 41, i32 62, i32 26, i32 24, i32 25, i32 18>
+  %s.16.0 = shufflevector <32 x i64> %s.15.0, <32 x i64> undef, <32 x i32> <i32 63, i32 62, i32 29, i32 3, i32 49, i32 5, i32 54, i32 9, i32 53, i32 15, i32 11, i32 20, i32 27, i32 17, i32 6, i32 52, i32 35, i32 40, i32 9, i32 36, i32 63, i32 13, i32 60, i32 30, i32 54, i32 26, i32 44, i32 18, i32 47, i32 45, i32 26, i32 33>
+  ret <32 x i64> %s.16.0
+}