From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 27 Jun 2017 18:28:10 +0000 (+0000)
Subject: RenameIndependentSubregs: Fix infinite loop
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=d841eae40bbc1c3c740394ef6b1948297de9c31a;p=llvm

RenameIndependentSubregs: Fix infinite loop

Apparently this replacement can really be substituting the
same as the original register. Avoid restarting the loop
when there's been no change in the register uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306441 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/RenameIndependentSubregs.cpp b/lib/CodeGen/RenameIndependentSubregs.cpp
index a5abd500080..bd5ecbd28f2 100644
--- a/lib/CodeGen/RenameIndependentSubregs.cpp
+++ b/lib/CodeGen/RenameIndependentSubregs.cpp
@@ -243,7 +243,8 @@ void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes,
 
     unsigned VReg = Intervals[ID]->reg;
     MO.setReg(VReg);
-    if (MO.isTied()) {
+
+    if (MO.isTied() && Reg != VReg) {
       /// Undef use operands are not tracked in the equivalence class but need
       /// to be update if they are tied.
       MO.getParent()->substituteRegister(Reg, VReg, 0, TRI);
diff --git a/test/CodeGen/AMDGPU/rename-independent-subregs-invalid-mac-operands.mir b/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
similarity index 88%
rename from test/CodeGen/AMDGPU/rename-independent-subregs-invalid-mac-operands.mir
rename to test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
index 9f20d2854c6..770bfaddb23 100644
--- a/test/CodeGen/AMDGPU/rename-independent-subregs-invalid-mac-operands.mir
+++ b/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
@@ -134,3 +134,22 @@ body:             |
     S_SETPC_B64_return %sgpr30_sgpr31, implicit %sgpr5
 
 ...
+
+# GCN-LABEL: name: inf_loop_tied_operand
+# GCN: bb.0:
+# GCN-NEXT: undef %2.sub0 = V_MAC_F32_e32 1073741824, undef %0, undef %2.sub0, implicit %exec
+# GCN-NEXT: dead undef %3.sub1 = COPY %2.sub0
+
+name:            inf_loop_tied_operand
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '' }
+  - { id: 1, class: vgpr_32, preferred-register: '' }
+  - { id: 2, class: vreg_128, preferred-register: '' }
+body:             |
+  bb.0:
+    %1 = V_MAC_F32_e32 1073741824, undef %0, undef %1, implicit %exec
+    undef %2.sub0 = COPY %1
+    %2.sub1 = COPY %1
+
+...