From: Roman Lebedev <lebedev.ri@gmail.com>
Date: Thu, 23 May 2019 18:08:17 +0000 (+0000)
Subject: [NFC][Mips] Autogenerate msa/i5-s.ll test
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=d73bf2e511473846ff542c9aac63c79e87a484b2;p=llvm

[NFC][Mips] Autogenerate msa/i5-s.ll test

Being affected by (sub %x, C) -> add %X, (sub 0, C) 'for vectors' patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361523 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/Mips/msa/i5-s.ll b/test/CodeGen/Mips/msa/i5-s.ll
index db331b1476c..ce5e4eb091b 100644
--- a/test/CodeGen/Mips/msa/i5-s.ll
+++ b/test/CodeGen/Mips/msa/i5-s.ll
@@ -1,13 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=ALL,MIPS
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL
+
 ; Test the MSA intrinsics that are encoded with the I5 instruction format.
 ; There are lots of these so this covers those beginning with 's'
 
-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
-
 @llvm_mips_subvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
 @llvm_mips_subvi_b_RES  = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
 
 define void @llvm_mips_subvi_b_test() nounwind {
+; ALL-LABEL: llvm_mips_subvi_b_test:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    lui $1, %hi(llvm_mips_subvi_b_RES)
+; ALL-NEXT:    addiu $1, $1, %lo(llvm_mips_subvi_b_RES)
+; ALL-NEXT:    lui $2, %hi(llvm_mips_subvi_b_ARG1)
+; ALL-NEXT:    addiu $2, $2, %lo(llvm_mips_subvi_b_ARG1)
+; ALL-NEXT:    ld.b $w0, 0($2)
+; ALL-NEXT:    subvi.b $w0, $w0, 14
+; ALL-NEXT:    jr $ra
+; ALL-NEXT:    st.b $w0, 0($1)
 entry:
   %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subvi_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.subvi.b(<16 x i8> %0, i32 14)
@@ -17,16 +28,20 @@ entry:
 
 declare <16 x i8> @llvm.mips.subvi.b(<16 x i8>, i32) nounwind
 
-; CHECK: llvm_mips_subvi_b_test:
-; CHECK: ld.b
-; CHECK: subvi.b
-; CHECK: st.b
-; CHECK: .size llvm_mips_subvi_b_test
-;
 @llvm_mips_subvi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
 @llvm_mips_subvi_h_RES  = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
 
 define void @llvm_mips_subvi_h_test() nounwind {
+; ALL-LABEL: llvm_mips_subvi_h_test:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    lui $1, %hi(llvm_mips_subvi_h_RES)
+; ALL-NEXT:    addiu $1, $1, %lo(llvm_mips_subvi_h_RES)
+; ALL-NEXT:    lui $2, %hi(llvm_mips_subvi_h_ARG1)
+; ALL-NEXT:    addiu $2, $2, %lo(llvm_mips_subvi_h_ARG1)
+; ALL-NEXT:    ld.h $w0, 0($2)
+; ALL-NEXT:    subvi.h $w0, $w0, 14
+; ALL-NEXT:    jr $ra
+; ALL-NEXT:    st.h $w0, 0($1)
 entry:
   %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subvi_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.subvi.h(<8 x i16> %0, i32 14)
@@ -36,16 +51,20 @@ entry:
 
 declare <8 x i16> @llvm.mips.subvi.h(<8 x i16>, i32) nounwind
 
-; CHECK: llvm_mips_subvi_h_test:
-; CHECK: ld.h
-; CHECK: subvi.h
-; CHECK: st.h
-; CHECK: .size llvm_mips_subvi_h_test
-;
 @llvm_mips_subvi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
 @llvm_mips_subvi_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
 
 define void @llvm_mips_subvi_w_test() nounwind {
+; ALL-LABEL: llvm_mips_subvi_w_test:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    lui $1, %hi(llvm_mips_subvi_w_RES)
+; ALL-NEXT:    addiu $1, $1, %lo(llvm_mips_subvi_w_RES)
+; ALL-NEXT:    lui $2, %hi(llvm_mips_subvi_w_ARG1)
+; ALL-NEXT:    addiu $2, $2, %lo(llvm_mips_subvi_w_ARG1)
+; ALL-NEXT:    ld.w $w0, 0($2)
+; ALL-NEXT:    subvi.w $w0, $w0, 14
+; ALL-NEXT:    jr $ra
+; ALL-NEXT:    st.w $w0, 0($1)
 entry:
   %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subvi_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.subvi.w(<4 x i32> %0, i32 14)
@@ -55,16 +74,20 @@ entry:
 
 declare <4 x i32> @llvm.mips.subvi.w(<4 x i32>, i32) nounwind
 
-; CHECK: llvm_mips_subvi_w_test:
-; CHECK: ld.w
-; CHECK: subvi.w
-; CHECK: st.w
-; CHECK: .size llvm_mips_subvi_w_test
-;
 @llvm_mips_subvi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
 @llvm_mips_subvi_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
 
 define void @llvm_mips_subvi_d_test() nounwind {
+; ALL-LABEL: llvm_mips_subvi_d_test:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    lui $1, %hi(llvm_mips_subvi_d_RES)
+; ALL-NEXT:    addiu $1, $1, %lo(llvm_mips_subvi_d_RES)
+; ALL-NEXT:    lui $2, %hi(llvm_mips_subvi_d_ARG1)
+; ALL-NEXT:    addiu $2, $2, %lo(llvm_mips_subvi_d_ARG1)
+; ALL-NEXT:    ld.d $w0, 0($2)
+; ALL-NEXT:    subvi.d $w0, $w0, 14
+; ALL-NEXT:    jr $ra
+; ALL-NEXT:    st.d $w0, 0($1)
 entry:
   %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subvi_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.subvi.d(<2 x i64> %0, i32 14)
@@ -73,10 +96,3 @@ entry:
 }
 
 declare <2 x i64> @llvm.mips.subvi.d(<2 x i64>, i32) nounwind
-
-; CHECK: llvm_mips_subvi_d_test:
-; CHECK: ld.d
-; CHECK: subvi.d
-; CHECK: st.d
-; CHECK: .size llvm_mips_subvi_d_test
-;