From: Sanjay Patel <spatel@rotateright.com>
Date: Wed, 25 Jul 2018 21:25:50 +0000 (+0000)
Subject: [AArch, PowerPC] add more tests for legal rotate ops; NFC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=d73322deb3b99030d7cdbf5b304a3fbacbb17a4a;p=llvm

[AArch, PowerPC] add more tests for legal rotate ops; NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337964 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/AArch64/funnel-shift-rot.ll b/test/CodeGen/AArch64/funnel-shift-rot.ll
index 5e9b0633e9b..0b3bc665bdf 100644
--- a/test/CodeGen/AArch64/funnel-shift-rot.ll
+++ b/test/CodeGen/AArch64/funnel-shift-rot.ll
@@ -64,6 +64,19 @@ define i32 @rotl_i32(i32 %x, i32 %z) {
   ret i32 %f
 }
 
+define i64 @rotl_i64(i64 %x, i64 %z) {
+; CHECK-LABEL: rotl_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    orr w9, wzr, #0x40
+; CHECK-NEXT:    sub w9, w9, w1
+; CHECK-NEXT:    lsl x8, x0, x1
+; CHECK-NEXT:    lsr x9, x0, x9
+; CHECK-NEXT:    orr x0, x8, x9
+; CHECK-NEXT:    ret
+  %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
+  ret i64 %f
+}
+
 ; Vector rotate.
 
 define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
@@ -138,6 +151,15 @@ define i16 @rotr_i16(i16 %x, i16 %z) {
   ret i16 %f
 }
 
+define i32 @rotr_i32(i32 %x, i32 %z) {
+; CHECK-LABEL: rotr_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ror w0, w0, w1
+; CHECK-NEXT:    ret
+  %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
+  ret i32 %f
+}
+
 define i64 @rotr_i64(i64 %x, i64 %z) {
 ; CHECK-LABEL: rotr_i64:
 ; CHECK:       // %bb.0:
diff --git a/test/CodeGen/PowerPC/funnel-shift-rot.ll b/test/CodeGen/PowerPC/funnel-shift-rot.ll
index 41317ed68d9..b238504edc1 100644
--- a/test/CodeGen/PowerPC/funnel-shift-rot.ll
+++ b/test/CodeGen/PowerPC/funnel-shift-rot.ll
@@ -62,13 +62,23 @@ define i32 @rotl_i32(i32 %x, i32 %z) {
   ret i32 %f
 }
 
+define i64 @rotl_i64(i64 %x, i64 %z) {
+; CHECK-LABEL: rotl_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rlwinm 4, 4, 0, 26, 31
+; CHECK-NEXT:    rotld 3, 3, 4
+; CHECK-NEXT:    blr
+  %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
+  ret i64 %f
+}
+
 ; Vector rotate.
 
 define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
 ; CHECK-LABEL: rotl_v4i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI4_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI5_0@toc@l
 ; CHECK-NEXT:    lvx 4, 0, 3
 ; CHECK-NEXT:    vsubuwm 4, 4, 3
 ; CHECK-NEXT:    vslw 3, 2, 3
@@ -135,6 +145,17 @@ define i16 @rotr_i16(i16 %x, i16 %z) {
   ret i16 %f
 }
 
+define i32 @rotr_i32(i32 %x, i32 %z) {
+; CHECK-LABEL: rotr_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    subfic 4, 4, 32
+; CHECK-NEXT:    clrlwi 4, 4, 27
+; CHECK-NEXT:    rlwnm 3, 3, 4, 0, 31
+; CHECK-NEXT:    blr
+  %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
+  ret i32 %f
+}
+
 define i64 @rotr_i64(i64 %x, i64 %z) {
 ; CHECK-LABEL: rotr_i64:
 ; CHECK:       # %bb.0:
@@ -151,8 +172,8 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
 define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
 ; CHECK-LABEL: rotr_v4i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI10_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI12_0@toc@l
 ; CHECK-NEXT:    lvx 4, 0, 3
 ; CHECK-NEXT:    vsubuwm 4, 4, 3
 ; CHECK-NEXT:    vsrw 3, 2, 3