From: Craig Topper Date: Tue, 4 Apr 2017 20:26:25 +0000 (+0000) Subject: [InstCombine] Support folding and/or/xor with a constant vector RHS into selects... X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=d6c407ebd68ac980ee78ebe14d510740152884fa;p=llvm [InstCombine] Support folding and/or/xor with a constant vector RHS into selects and phis Currently we only fold with ConstantInt RHS. This generalizes to any Constant RHS. Differential Revision: https://reviews.llvm.org/D31610 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299466 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 5f16284631e..41395c6bbe6 100644 --- a/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -1403,10 +1403,11 @@ Instruction *InstCombiner::visitAnd(BinaryOperator &I) { return BinaryOperator::CreateAnd(NewCast, C3); } } + } + if (isa(Op1)) if (Instruction *FoldedLogic = foldOpWithConstantIntoOperand(I)) return FoldedLogic; - } if (Instruction *DeMorgan = matchDeMorgansLaws(I, Builder)) return DeMorgan; @@ -2130,10 +2131,11 @@ Instruction *InstCombiner::visitOr(BinaryOperator &I) { return BinaryOperator::CreateXor(Or, Builder->getInt(C1->getValue() & ~RHS->getValue())); } + } + if (isa(Op1)) if (Instruction *FoldedLogic = foldOpWithConstantIntoOperand(I)) return FoldedLogic; - } // Given an OR instruction, check to see if this is a bswap. if (Instruction *BSwap = MatchBSwap(I)) @@ -2593,10 +2595,11 @@ Instruction *InstCombiner::visitXor(BinaryOperator &I) { } } } + } + if (isa(Op1)) if (Instruction *FoldedLogic = foldOpWithConstantIntoOperand(I)) return FoldedLogic; - } BinaryOperator *Op1I = dyn_cast(Op1); if (Op1I) { diff --git a/test/Transforms/InstCombine/and.ll b/test/Transforms/InstCombine/and.ll index 34285a2a657..f9cae942b3a 100644 --- a/test/Transforms/InstCombine/and.ll +++ b/test/Transforms/InstCombine/and.ll @@ -517,8 +517,7 @@ define <2 x i32> @test40vec(i1 %C) { define <2 x i32> @test40vec2(i1 %C) { ; CHECK-LABEL: @test40vec2( -; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], <2 x i32> , <2 x i32> -; CHECK-NEXT: [[V:%.*]] = and <2 x i32> [[A]], +; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> , <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[V]] ; %A = select i1 %C, <2 x i32> , <2 x i32> @@ -555,9 +554,8 @@ define <2 x i32> @test41vec(i1 %which) { ; CHECK: delay: ; CHECK-NEXT: br label [[FINAL]] ; CHECK: final: -; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] -; CHECK-NEXT: [[VALUE:%.*]] = and <2 x i32> [[A]], -; CHECK-NEXT: ret <2 x i32> [[VALUE]] +; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] +; CHECK-NEXT: ret <2 x i32> [[A]] ; entry: br i1 %which, label %final, label %delay @@ -578,9 +576,8 @@ define <2 x i32> @test41vec2(i1 %which) { ; CHECK: delay: ; CHECK-NEXT: br label [[FINAL]] ; CHECK: final: -; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] -; CHECK-NEXT: [[VALUE:%.*]] = and <2 x i32> [[A]], -; CHECK-NEXT: ret <2 x i32> [[VALUE]] +; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] +; CHECK-NEXT: ret <2 x i32> [[A]] ; entry: br i1 %which, label %final, label %delay diff --git a/test/Transforms/InstCombine/or.ll b/test/Transforms/InstCombine/or.ll index ded9ad8354e..2600136649a 100644 --- a/test/Transforms/InstCombine/or.ll +++ b/test/Transforms/InstCombine/or.ll @@ -714,8 +714,7 @@ define i32 @test49(i1 %C) { define <2 x i32> @test49vec(i1 %C) { ; CHECK-LABEL: @test49vec( -; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], <2 x i32> , <2 x i32> zeroinitializer -; CHECK-NEXT: [[V:%.*]] = or <2 x i32> [[A]], +; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> , <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[V]] ; %A = select i1 %C, <2 x i32> , <2 x i32> @@ -725,8 +724,7 @@ define <2 x i32> @test49vec(i1 %C) { define <2 x i32> @test49vec2(i1 %C) { ; CHECK-LABEL: @test49vec2( -; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], <2 x i32> , <2 x i32> -; CHECK-NEXT: [[V:%.*]] = or <2 x i32> [[A]], +; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> , <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[V]] ; %A = select i1 %C, <2 x i32> , <2 x i32> @@ -763,9 +761,8 @@ define <2 x i32> @test50vec(i1 %which) { ; CHECK: delay: ; CHECK-NEXT: br label [[FINAL]] ; CHECK: final: -; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] -; CHECK-NEXT: [[VALUE:%.*]] = or <2 x i32> [[A]], -; CHECK-NEXT: ret <2 x i32> [[VALUE]] +; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] +; CHECK-NEXT: ret <2 x i32> [[A]] ; entry: br i1 %which, label %final, label %delay @@ -786,9 +783,8 @@ define <2 x i32> @test50vec2(i1 %which) { ; CHECK: delay: ; CHECK-NEXT: br label [[FINAL]] ; CHECK: final: -; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] -; CHECK-NEXT: [[VALUE:%.*]] = or <2 x i32> [[A]], -; CHECK-NEXT: ret <2 x i32> [[VALUE]] +; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] +; CHECK-NEXT: ret <2 x i32> [[A]] ; entry: br i1 %which, label %final, label %delay diff --git a/test/Transforms/InstCombine/xor.ll b/test/Transforms/InstCombine/xor.ll index 699c1994be1..b5fbfabbda2 100644 --- a/test/Transforms/InstCombine/xor.ll +++ b/test/Transforms/InstCombine/xor.ll @@ -365,8 +365,7 @@ define i32 @test29(i1 %C) { define <2 x i32> @test29vec(i1 %C) { ; CHECK-LABEL: @test29vec( -; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], <2 x i32> , <2 x i32> -; CHECK-NEXT: [[V:%.*]] = xor <2 x i32> [[A]], +; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> , <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[V]] ; %A = select i1 %C, <2 x i32> , <2 x i32> @@ -376,8 +375,7 @@ define <2 x i32> @test29vec(i1 %C) { define <2 x i32> @test29vec2(i1 %C) { ; CHECK-LABEL: @test29vec2( -; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], <2 x i32> , <2 x i32> -; CHECK-NEXT: [[V:%.*]] = xor <2 x i32> [[A]], +; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> , <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[V]] ; %A = select i1 %C, <2 x i32> , <2 x i32> @@ -414,9 +412,8 @@ define <2 x i32> @test30vec(i1 %which) { ; CHECK: delay: ; CHECK-NEXT: br label [[FINAL]] ; CHECK: final: -; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] -; CHECK-NEXT: [[VALUE:%.*]] = xor <2 x i32> [[A]], -; CHECK-NEXT: ret <2 x i32> [[VALUE]] +; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] +; CHECK-NEXT: ret <2 x i32> [[A]] ; entry: br i1 %which, label %final, label %delay @@ -437,9 +434,8 @@ define <2 x i32> @test30vec2(i1 %which) { ; CHECK: delay: ; CHECK-NEXT: br label [[FINAL]] ; CHECK: final: -; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] -; CHECK-NEXT: [[VALUE:%.*]] = xor <2 x i32> [[A]], -; CHECK-NEXT: ret <2 x i32> [[VALUE]] +; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ , [[ENTRY:%.*]] ], [ , [[DELAY]] ] +; CHECK-NEXT: ret <2 x i32> [[A]] ; entry: br i1 %which, label %final, label %delay