From: Kewen Lin <jedilyn@163.com>
Date: Tue, 18 Dec 2018 08:11:32 +0000 (+0000)
Subject: [PowerPC][NFC]Update vabsd cases with vselect test cases
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=d662b7528654349d3b9e96eb7017efeb06583f90;p=llvm

[PowerPC][NFC]Update vabsd cases with vselect test cases

Power9 VABSDU* instructions can be exploited for some special vselect sequences.
Check in the orignal test case here, later the exploitation patch will update this
and reviewers can check the differences easily.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349446 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll b/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
index 6b1c6e398d8..faa731fd0fe 100644
--- a/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
+++ b/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
@@ -517,6 +517,200 @@ define <16 x i8> @zext_sub_absd8(<16 x i4>, <16 x i4>) local_unnamed_addr {
 ; CHECK-PWR8: blr
 }
 
+; To verify vabsdu* exploitation for ucmp + sub + select sequence
+
+define <4 x i32> @absd_int32_ugt(<4 x i32>, <4 x i32>) {
+  %3 = icmp ugt <4 x i32> %0, %1
+  %4 = sub <4 x i32> %0, %1
+  %5 = sub <4 x i32> %1, %0
+  %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
+  ret <4 x i32> %6
+; CHECK-LABEL: absd_int32_ugt
+; CHECK: vcmpgtuw
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int32_ugt
+; CHECK-PWR8: vcmpgtuw
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
+define <4 x i32> @absd_int32_uge(<4 x i32>, <4 x i32>) {
+  %3 = icmp uge <4 x i32> %0, %1
+  %4 = sub <4 x i32> %0, %1
+  %5 = sub <4 x i32> %1, %0
+  %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
+  ret <4 x i32> %6
+; CHECK-LABEL: absd_int32_uge
+; CHECK: vcmpgtuw
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int32_uge
+; CHECK-PWR8: vcmpgtuw
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
+define <4 x i32> @absd_int32_ult(<4 x i32>, <4 x i32>) {
+  %3 = icmp ult <4 x i32> %0, %1
+  %4 = sub <4 x i32> %0, %1
+  %5 = sub <4 x i32> %1, %0
+  %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
+  ret <4 x i32> %6
+; CHECK-LABEL: absd_int32_ult
+; CHECK: vcmpgtuw
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int32_ult
+; CHECK-PWR8: vcmpgtuw
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
+define <4 x i32> @absd_int32_ule(<4 x i32>, <4 x i32>) {
+  %3 = icmp ule <4 x i32> %0, %1
+  %4 = sub <4 x i32> %0, %1
+  %5 = sub <4 x i32> %1, %0
+  %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
+  ret <4 x i32> %6
+; CHECK-LABEL: absd_int32_ule
+; CHECK: vcmpgtuw
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int32_ule
+; CHECK-PWR8: vcmpgtuw
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
+define <8 x i16> @absd_int16_ugt(<8 x i16>, <8 x i16>) {
+  %3 = icmp ugt <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
+  ret <8 x i16> %6
+; CHECK-LABEL: absd_int16_ugt
+; CHECK: vcmpgtuh
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int16_ugt
+; CHECK-PWR8: vcmpgtuh
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
+define <8 x i16> @absd_int16_uge(<8 x i16>, <8 x i16>) {
+  %3 = icmp uge <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
+  ret <8 x i16> %6
+; CHECK-LABEL: absd_int16_uge
+; CHECK: vcmpgtuh
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int16_uge
+; CHECK-PWR8: vcmpgtuh
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
+define <8 x i16> @absd_int16_ult(<8 x i16>, <8 x i16>) {
+  %3 = icmp ult <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
+  ret <8 x i16> %6
+; CHECK-LABEL: absd_int16_ult
+; CHECK: vcmpgtuh
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int16_ult
+; CHECK-PWR8: vcmpgtuh
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
+define <8 x i16> @absd_int16_ule(<8 x i16>, <8 x i16>) {
+  %3 = icmp ule <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
+  ret <8 x i16> %6
+; CHECK-LABEL: absd_int16_ule
+; CHECK: vcmpgtuh
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int16_ule
+; CHECK-PWR8: vcmpgtuh
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
+define <16 x i8> @absd_int8_ugt(<16 x i8>, <16 x i8>) {
+  %3 = icmp ugt <16 x i8> %0, %1
+  %4 = sub <16 x i8> %0, %1
+  %5 = sub <16 x i8> %1, %0
+  %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
+  ret <16 x i8> %6
+; CHECK-LABEL: absd_int8_ugt
+; CHECK: vcmpgtub
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int8_ugt
+; CHECK-PWR8: vcmpgtub
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
+define <16 x i8> @absd_int8_uge(<16 x i8>, <16 x i8>) {
+  %3 = icmp uge <16 x i8> %0, %1
+  %4 = sub <16 x i8> %0, %1
+  %5 = sub <16 x i8> %1, %0
+  %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
+  ret <16 x i8> %6
+; CHECK-LABEL: absd_int8_uge
+; CHECK: vcmpgtub
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int8_uge
+; CHECK-PWR8: vcmpgtub
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
+define <16 x i8> @absd_int8_ult(<16 x i8>, <16 x i8>) {
+  %3 = icmp ult <16 x i8> %0, %1
+  %4 = sub <16 x i8> %0, %1
+  %5 = sub <16 x i8> %1, %0
+  %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
+  ret <16 x i8> %6
+; CHECK-LABEL: absd_int8_ult
+; CHECK: vcmpgtub
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int8_ult
+; CHECK-PWR8: vcmpgtub
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
+define <16 x i8> @absd_int8_ule(<16 x i8>, <16 x i8>) {
+  %3 = icmp ule <16 x i8> %0, %1
+  %4 = sub <16 x i8> %0, %1
+  %5 = sub <16 x i8> %1, %0
+  %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
+  ret <16 x i8> %6
+; CHECK-LABEL: absd_int8_ule
+; CHECK: vcmpgtub
+; CHECK: xxsel
+; CHECK: blr
+; CHECK-PWR8-LABEL: absd_int8_ule
+; CHECK-PWR8: vcmpgtub
+; CHECK-PWR8: xxsel
+; CHECK-PWR8: blr
+}
+
 declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>)
 
 declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>)