From: Craig Topper <craig.topper@intel.com>
Date: Wed, 4 Sep 2019 16:01:43 +0000 (+0000)
Subject: [X86] Add support for avx512bf16 for __builtin_cpu_supports and compiler-rt's cpu... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=d65619850cf818605ea97e205a363c519b566358;p=llvm

[X86] Add support for avx512bf16 for __builtin_cpu_supports and compiler-rt's cpu indicator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370915 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/Support/X86TargetParser.def b/include/llvm/Support/X86TargetParser.def
index a4ed8ee21c9..4ebf2d79cb8 100644
--- a/include/llvm/Support/X86TargetParser.def
+++ b/include/llvm/Support/X86TargetParser.def
@@ -161,13 +161,13 @@ X86_FEATURE_COMPAT(32, FEATURE_GFNI,            "gfni")
 X86_FEATURE_COMPAT(33, FEATURE_VPCLMULQDQ,      "vpclmulqdq")
 X86_FEATURE_COMPAT(34, FEATURE_AVX512VNNI,      "avx512vnni")
 X86_FEATURE_COMPAT(35, FEATURE_AVX512BITALG,    "avx512bitalg")
+X86_FEATURE_COMPAT(36, FEATURE_AVX512BF16,      "avx512bf16")
 // Features below here are not in libgcc/compiler-rt.
 X86_FEATURE       (64, FEATURE_MOVBE)
 X86_FEATURE       (65, FEATURE_ADX)
 X86_FEATURE       (66, FEATURE_EM64T)
 X86_FEATURE       (67, FEATURE_CLFLUSHOPT)
 X86_FEATURE       (68, FEATURE_SHA)
-X86_FEATURE       (69, FEATURE_AVX512BF16)
-X86_FEATURE       (70, FEATURE_AVX512VP2INTERSECT)
+X86_FEATURE       (69, FEATURE_AVX512VP2INTERSECT)
 #undef X86_FEATURE_COMPAT
 #undef X86_FEATURE
diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp
index ef10b9689e8..0d6fab50424 100644
--- a/lib/Support/Host.cpp
+++ b/lib/Support/Host.cpp
@@ -680,7 +680,7 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
     // Skylake Xeon:
     case 0x55:
       *Type = X86::INTEL_COREI7;
-      if (Features3 & (1 << (X86::FEATURE_AVX512BF16 - 64)))
+      if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32)))
         *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake"
       else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32)))
         *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake"
@@ -765,7 +765,7 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
         break;
       }
 
-      if (Features3 & (1 << (X86::FEATURE_AVX512BF16 - 64))) {
+      if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) {
         *Type = X86::INTEL_COREI7;
         *Subtype = X86::INTEL_COREI7_COOPERLAKE;
         break;
@@ -1088,6 +1088,11 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
   if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
     setFeature(X86::FEATURE_AVX512VP2INTERSECT);
 
+  bool HasLeaf7Subleaf1 =
+      MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
+  if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
+    setFeature(X86::FEATURE_AVX512BF16);
+
   unsigned MaxExtLevel;
   getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);