From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Fri, 3 Mar 2017 14:25:46 +0000 (+0000)
Subject: Use APInt::getOneBitSet instead of APInt::getBitsSet for sign bit mask creation
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=d3f4ec484266dfc49e1a102160e3fdfee304d352;p=llvm

Use APInt::getOneBitSet instead of APInt::getBitsSet for sign bit mask creation

Avoids all the unnecessary extra bitrange creation/shift stages.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296871 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 52551e7833c..8ac41197b62 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7702,7 +7702,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
   }
 
   // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
-  if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
+  if (DAG.MaskedValueIsZero(N0, APInt::getOneBitSet(VTBits, EVTBits - 1)))
     return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT.getScalarType());
 
   // fold operands of sext_in_reg based on knowledge that the top bits are not