From: Craig Topper Date: Mon, 11 Mar 2019 22:29:00 +0000 (+0000) Subject: [X86] Remove ProcModel and ProcFeatures tablegen classes. Move all feature lists... X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=d332bc44067211588dc215c1b93e007ea30abb2f;p=llvm [X86] Remove ProcModel and ProcFeatures tablegen classes. Move all feature lists into a ProcessorFeatures class. ProcFeatures was a class that just concatenated two feature lists together and gave it a name. We used it to inherit features between CPUs. ProcModel took a two CPU feature lists and concatenated them before deferring to ProcessorModel. This was to allow inherited features and specific features to be passed to each CPU. Both of these allowed for only very rigid CPU inheritance rules. With this patch we now store all of the lists we were using for inheritance in one object and do any list oncatenation we want there. Then we just pass whatever list we want from this class into the ProcessorModel class for each CPU. Hopefully this gives us more flexibility to build up feature lists in whatever ways we think make sense. Perhaps untangling ISA flags and tuning flags. I've only touched the CPUs that were directly affected by the removal of the ProcModel and ProcFeatures classes. We should move more of the feature lists into ProcessorFeatures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355872 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index b3a9b9591ee..c25235f377e 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -421,6 +421,17 @@ def FeatureMergeToThreeWayBranch : SubtargetFeature<"merge-to-threeway-branch", "Merge branches to a three-way " "conditional branch">; +// Bonnell +def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">; +// Silvermont +def ProcIntelSLM : SubtargetFeature<"", "X86ProcFamily", "IntelSLM", "">; +// Goldmont +def ProcIntelGLM : SubtargetFeature<"", "X86ProcFamily", "IntelGLM", "">; +// Goldmont Plus +def ProcIntelGLP : SubtargetFeature<"", "X86ProcFamily", "IntelGLP", "">; +// Tremont +def ProcIntelTRM : SubtargetFeature<"", "X86ProcFamily", "IntelTRM", "">; + //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// @@ -439,7 +450,7 @@ include "X86SchedPredicates.td" def X86InstrInfo : InstrInfo; //===----------------------------------------------------------------------===// -// X86 processors supported. +// X86 Scheduler Models //===----------------------------------------------------------------------===// include "X86ScheduleAtom.td" @@ -453,16 +464,299 @@ include "X86ScheduleBtVer2.td" include "X86SchedSkylakeClient.td" include "X86SchedSkylakeServer.td" -// Bonnell -def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">; -// Silvermont -def ProcIntelSLM : SubtargetFeature<"", "X86ProcFamily", "IntelSLM", "">; -// Goldmont -def ProcIntelGLM : SubtargetFeature<"", "X86ProcFamily", "IntelGLM", "">; -// Goldmont Plus -def ProcIntelGLP : SubtargetFeature<"", "X86ProcFamily", "IntelGLP", "">; -// Tremont -def ProcIntelTRM : SubtargetFeature<"", "X86ProcFamily", "IntelTRM", "">; +//===----------------------------------------------------------------------===// +// X86 Processor Feature Lists +//===----------------------------------------------------------------------===// + +def ProcessorFeatures { + // Sandybridge + // SSE is not listed here since llvm treats AVX as a reimplementation of SSE, + // rather than a superset. + list SNBInheritableFeatures = [FeatureX87, + FeatureCMOV, + FeatureMMX, + FeatureAVX, + FeatureFXSR, + FeatureNOPL, + Feature64Bit, + FeatureCMPXCHG16B, + FeaturePOPCNT, + FeatureSlowDivide64, + FeaturePCLMUL, + FeatureXSAVE, + FeatureXSAVEOPT, + FeatureLAHFSAHF, + FeatureSlow3OpsLEA, + FeatureFastScalarFSQRT, + FeatureFastSHLDRotate, + FeatureMergeToThreeWayBranch, + FeatureMacroFusion]; + list SNBSpecificFeatures = [FeatureSlowUAMem32, + FeaturePOPCNTFalseDeps]; + list SNBFeatures = + !listconcat(SNBInheritableFeatures, SNBSpecificFeatures); + + // Ivybridge + list IVBAdditionalFeatures = [FeatureRDRAND, + FeatureF16C, + FeatureFSGSBase]; + list IVBSpecificFeatures = [FeatureSlowUAMem32, + FeaturePOPCNTFalseDeps]; + list IVBInheritableFeatures = + !listconcat(SNBInheritableFeatures, IVBAdditionalFeatures); + list IVBFeatures = + !listconcat(IVBInheritableFeatures, IVBSpecificFeatures); + + // Haswell + list HSWAdditionalFeatures = [FeatureAVX2, + FeatureBMI, + FeatureBMI2, + FeatureERMSB, + FeatureFMA, + FeatureINVPCID, + FeatureLZCNT, + FeatureMOVBE, + FeatureFastVariableShuffle]; + list HSWSpecificFeatures = [FeaturePOPCNTFalseDeps, + FeatureLZCNTFalseDeps]; + list HSWInheritableFeatures = + !listconcat(IVBInheritableFeatures, HSWAdditionalFeatures); + list HSWFeatures = + !listconcat(HSWInheritableFeatures, HSWSpecificFeatures); + + // Broadwell + list BDWAdditionalFeatures = [FeatureADX, + FeatureRDSEED, + FeaturePRFCHW]; + list BDWSpecificFeatures = [FeaturePOPCNTFalseDeps, + FeatureLZCNTFalseDeps]; + list BDWInheritableFeatures = + !listconcat(HSWInheritableFeatures, BDWAdditionalFeatures); + list BDWFeatures = + !listconcat(BDWInheritableFeatures, BDWSpecificFeatures); + + // Skylake + list SKLAdditionalFeatures = [FeatureAES, + FeatureMPX, + FeatureXSAVEC, + FeatureXSAVES, + FeatureCLFLUSHOPT, + FeatureFastVectorFSQRT]; + list SKLSpecificFeatures = [FeatureHasFastGather, + FeaturePOPCNTFalseDeps, + FeatureSGX]; + list SKLInheritableFeatures = + !listconcat(BDWInheritableFeatures, SKLAdditionalFeatures); + list SKLFeatures = + !listconcat(SKLInheritableFeatures, SKLSpecificFeatures); + + // Skylake-AVX512 + list SKXAdditionalFeatures = [FeatureAVX512, + FeatureCDI, + FeatureDQI, + FeatureBWI, + FeatureVLX, + FeaturePKU, + FeatureCLWB]; + list SKXSpecificFeatures = [FeatureHasFastGather, + FeaturePOPCNTFalseDeps]; + list SKXInheritableFeatures = + !listconcat(SKLInheritableFeatures, SKXAdditionalFeatures); + list SKXFeatures = + !listconcat(SKXInheritableFeatures, SKXSpecificFeatures); + + // Cascadelake + list CLXAdditionalFeatures = [FeatureVNNI]; + list CLXSpecificFeatures = [FeatureHasFastGather, + FeaturePOPCNTFalseDeps]; + list CLXInheritableFeatures = + !listconcat(SKXInheritableFeatures, CLXAdditionalFeatures); + list CLXFeatures = + !listconcat(CLXInheritableFeatures, CLXSpecificFeatures); + + // Cannonlake + list CNLAdditionalFeatures = [FeatureAVX512, + FeatureCDI, + FeatureDQI, + FeatureBWI, + FeatureVLX, + FeaturePKU, + FeatureVBMI, + FeatureIFMA, + FeatureSHA, + FeatureSGX]; + list CNLSpecificFeatures = [FeatureHasFastGather]; + list CNLInheritableFeatures = + !listconcat(SKLInheritableFeatures, CNLAdditionalFeatures); + list CNLFeatures = + !listconcat(CNLInheritableFeatures, CNLSpecificFeatures); + + // Icelake + list ICLAdditionalFeatures = [FeatureBITALG, + FeatureVAES, + FeatureVBMI2, + FeatureVNNI, + FeatureVPCLMULQDQ, + FeatureVPOPCNTDQ, + FeatureGFNI, + FeatureCLWB, + FeatureRDPID]; + list ICLSpecificFeatures = [FeatureHasFastGather]; + list ICLInheritableFeatures = + !listconcat(CNLInheritableFeatures, ICLAdditionalFeatures); + list ICLFeatures = + !listconcat(ICLInheritableFeatures, ICLSpecificFeatures); + + // Icelake Server + list ICXSpecificFeatures = [FeaturePCONFIG, + FeatureWBNOINVD, + FeatureHasFastGather]; + list ICXFeatures = + !listconcat(ICLInheritableFeatures, ICXSpecificFeatures); + + // Goldmont + list GLMInheritableFeatures = [FeatureX87, + FeatureCMOV, + FeatureMMX, + FeatureSSE42, + FeatureFXSR, + FeatureNOPL, + Feature64Bit, + FeatureCMPXCHG16B, + FeatureMOVBE, + FeaturePOPCNT, + FeaturePCLMUL, + FeatureAES, + FeaturePRFCHW, + FeatureSlowTwoMemOps, + FeatureSlowLEA, + FeatureSlowIncDec, + FeatureLAHFSAHF, + FeatureMPX, + FeatureSHA, + FeatureRDRAND, + FeatureRDSEED, + FeatureXSAVE, + FeatureXSAVEOPT, + FeatureXSAVEC, + FeatureXSAVES, + FeatureCLFLUSHOPT, + FeatureFSGSBase]; + list GLMSpecificFeatures = [ProcIntelGLM, + FeaturePOPCNTFalseDeps]; + list GLMFeatures = + !listconcat(GLMInheritableFeatures, GLMSpecificFeatures); + + // Goldmont Plus + list GLPAdditionalFeatures = [FeaturePTWRITE, + FeatureRDPID, + FeatureSGX]; + list GLPSpecificFeatures = [ProcIntelGLP]; + list GLPInheritableFeatures = + !listconcat(GLMInheritableFeatures, GLPAdditionalFeatures); + list GLPFeatures = + !listconcat(GLPInheritableFeatures, GLPSpecificFeatures); + + // Tremont + list TRMAdditionalFeatures = [FeatureCLDEMOTE, + FeatureGFNI, + FeatureMOVDIRI, + FeatureMOVDIR64B, + FeatureWAITPKG]; + list TRMSpecificFeatures = [ProcIntelTRM]; + list TRMFeatures = + !listconcat(GLPInheritableFeatures, TRMAdditionalFeatures, + TRMSpecificFeatures); + + // Knights Landing + list KNLFeatures = [FeatureX87, + FeatureCMOV, + FeatureMMX, + FeatureFXSR, + FeatureNOPL, + Feature64Bit, + FeatureCMPXCHG16B, + FeaturePOPCNT, + FeatureSlowDivide64, + FeaturePCLMUL, + FeatureXSAVE, + FeatureXSAVEOPT, + FeatureLAHFSAHF, + FeatureSlow3OpsLEA, + FeatureSlowIncDec, + FeatureAES, + FeatureRDRAND, + FeatureF16C, + FeatureFSGSBase, + FeatureAVX512, + FeatureERI, + FeatureCDI, + FeaturePFI, + FeaturePREFETCHWT1, + FeatureADX, + FeatureRDSEED, + FeatureMOVBE, + FeatureLZCNT, + FeatureBMI, + FeatureBMI2, + FeatureFMA, + FeaturePRFCHW, + FeatureSlowTwoMemOps, + FeatureFastPartialYMMorZMMWrite, + FeatureHasFastGather, + FeatureSlowPMADDWD]; + // TODO Add AVX5124FMAPS/AVX5124VNNIW features + list KNMFeatures = + !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]); + + // AMD Zen Processors common ISAs + list ZNFeatures = [FeatureADX, + FeatureAES, + FeatureAVX2, + FeatureBMI, + FeatureBMI2, + FeatureCLFLUSHOPT, + FeatureCLZERO, + FeatureCMOV, + Feature64Bit, + FeatureCMPXCHG16B, + FeatureF16C, + FeatureFMA, + FeatureFSGSBase, + FeatureFXSR, + FeatureNOPL, + FeatureFastLZCNT, + FeatureLAHFSAHF, + FeatureLZCNT, + FeatureFastBEXTR, + FeatureFast15ByteNOP, + FeatureMacroFusion, + FeatureMMX, + FeatureMOVBE, + FeatureMWAITX, + FeaturePCLMUL, + FeaturePOPCNT, + FeaturePRFCHW, + FeatureRDRAND, + FeatureRDSEED, + FeatureSHA, + FeatureSSE4A, + FeatureSlowSHLD, + FeatureX87, + FeatureXSAVE, + FeatureXSAVEC, + FeatureXSAVEOPT, + FeatureXSAVES]; + list ZN2AdditionalFeatures = [FeatureCLWB, + FeatureRDPID, + FeatureWBNOINVD]; + list ZN2Features = + !listconcat(ZNFeatures, ZN2AdditionalFeatures); +} + +//===----------------------------------------------------------------------===// +// X86 processors supported. +//===----------------------------------------------------------------------===// class Proc Features> : ProcessorModel; @@ -559,7 +853,8 @@ def : ProcessorModel<"penryn", SandyBridgeModel, [ ]>; // Atom CPUs. -class BonnellProc : ProcessorModel : ProcessorModel; -def : BonnellProc<"bonnell">; -def : BonnellProc<"atom">; // Pin the generic name to the baseline. - -class SilvermontProc : ProcessorModel; -def : SilvermontProc<"silvermont">; -def : SilvermontProc<"slm">; // Legacy alias. - -class ProcessorFeatures Inherited, - list NewFeatures> { - list Value = !listconcat(Inherited, NewFeatures); } -class ProcModel ProcFeatures, - list OtherFeatures> : - ProcessorModel; - -def GLMFeatures : ProcessorFeatures<[], [ - FeatureX87, - FeatureCMOV, - FeatureMMX, - FeatureSSE42, - FeatureFXSR, - FeatureNOPL, - Feature64Bit, - FeatureCMPXCHG16B, - FeatureMOVBE, - FeaturePOPCNT, - FeaturePCLMUL, - FeatureAES, - FeaturePRFCHW, - FeatureSlowTwoMemOps, - FeatureSlowLEA, - FeatureSlowIncDec, - FeatureLAHFSAHF, - FeatureMPX, - FeatureSHA, - FeatureRDRAND, - FeatureRDSEED, - FeatureXSAVE, - FeatureXSAVEOPT, - FeatureXSAVEC, - FeatureXSAVES, - FeatureCLFLUSHOPT, - FeatureFSGSBase -]>; - -class GoldmontProc : ProcModel; -def : GoldmontProc<"goldmont">; - -def GLPFeatures : ProcessorFeatures; +foreach P = ["silvermont", "slm"] in { + def : ProcessorModel; +} -class GoldmontPlusProc : ProcModel; -def : GoldmontPlusProc<"goldmont-plus">; - -class TremontProc : ProcModel; -def : TremontProc<"tremont">; +def : ProcessorModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures>; +def : ProcessorModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures>; +def : ProcessorModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures>; // "Arrandale" along with corei3 and corei5 -class NehalemProc : ProcessorModel; -def : NehalemProc<"nehalem">; -def : NehalemProc<"corei7">; +foreach P = ["nehalem", "corei7"] in { + def : ProcessorModel; +} // Westmere is a similar machine to nehalem with some additional features. // Westmere is the corei3/i5/i7 path from nehalem to sandybridge -class WestmereProc : ProcessorModel : ProcessorModel; -def : WestmereProc<"westmere">; - -// SSE is not listed here since llvm treats AVX as a reimplementation of SSE, -// rather than a superset. -def SNBFeatures : ProcessorFeatures<[], [ - FeatureX87, - FeatureCMOV, - FeatureMMX, - FeatureAVX, - FeatureFXSR, - FeatureNOPL, - Feature64Bit, - FeatureCMPXCHG16B, - FeaturePOPCNT, - FeatureSlowDivide64, - FeaturePCLMUL, - FeatureXSAVE, - FeatureXSAVEOPT, - FeatureLAHFSAHF, - FeatureSlow3OpsLEA, - FeatureFastScalarFSQRT, - FeatureFastSHLDRotate, - FeatureMergeToThreeWayBranch, - FeatureMacroFusion -]>; - -class SandyBridgeProc : ProcModel; -def : SandyBridgeProc<"sandybridge">; -def : SandyBridgeProc<"corei7-avx">; // Legacy alias. - -def IVBFeatures : ProcessorFeatures; - -class IvyBridgeProc : ProcModel; -def : IvyBridgeProc<"ivybridge">; -def : IvyBridgeProc<"core-avx-i">; // Legacy alias. - -def HSWFeatures : ProcessorFeatures; - -class HaswellProc : ProcModel; -def : HaswellProc<"haswell">; -def : HaswellProc<"core-avx2">; // Legacy alias. - -def BDWFeatures : ProcessorFeatures; -class BroadwellProc : ProcModel; -def : BroadwellProc<"broadwell">; - -def SKLFeatures : ProcessorFeatures; - -class SkylakeClientProc : ProcModel; -def : SkylakeClientProc<"skylake">; - -def KNLFeatures : ProcessorFeatures<[], [ - FeatureX87, - FeatureCMOV, - FeatureMMX, - FeatureFXSR, - FeatureNOPL, - Feature64Bit, - FeatureCMPXCHG16B, - FeaturePOPCNT, - FeatureSlowDivide64, - FeaturePCLMUL, - FeatureXSAVE, - FeatureXSAVEOPT, - FeatureLAHFSAHF, - FeatureSlow3OpsLEA, - FeatureSlowIncDec, - FeatureAES, - FeatureRDRAND, - FeatureF16C, - FeatureFSGSBase, - FeatureAVX512, - FeatureERI, - FeatureCDI, - FeaturePFI, - FeaturePREFETCHWT1, - FeatureADX, - FeatureRDSEED, - FeatureMOVBE, - FeatureLZCNT, - FeatureBMI, - FeatureBMI2, - FeatureFMA, - FeaturePRFCHW -]>; -// FIXME: define KNL model -class KnightsLandingProc : ProcModel; -def : KnightsLandingProc<"knl">; +foreach P = ["sandybridge", "corei7-avx"] in { + def : ProcessorModel; +} -class KnightsMillProc : ProcModel; -def : KnightsMillProc<"knm">; // TODO Add AVX5124FMAPS/AVX5124VNNIW features - -def SKXFeatures : ProcessorFeatures; +foreach P = ["ivybridge", "core-avx-i"] in { + def : ProcessorModel; +} -class SkylakeServerProc : ProcModel; -def : SkylakeServerProc<"skylake-avx512">; -def : SkylakeServerProc<"skx">; // Legacy alias. +foreach P = ["haswell", "core-avx2"] in { + def : ProcessorModel; +} -def CLXFeatures : ProcessorFeatures; +def : ProcessorModel<"broadwell", BroadwellModel, + ProcessorFeatures.BDWFeatures>; -class CascadelakeProc : ProcModel; -def : CascadelakeProc<"cascadelake">; - -def CNLFeatures : ProcessorFeatures; +def : ProcessorModel<"skylake", SkylakeClientModel, + ProcessorFeatures.SKLFeatures>; -class CannonlakeProc : ProcModel; -def : CannonlakeProc<"cannonlake">; - -def ICLFeatures : ProcessorFeatures; +// FIXME: define KNL scheduler model +def : ProcessorModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures>; +def : ProcessorModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures>; -class IcelakeClientProc : ProcModel; -def : IcelakeClientProc<"icelake-client">; +foreach P = ["skylake-avx512", "skx"] in { + def : ProcessorModel; +} -class IcelakeServerProc : ProcModel; -def : IcelakeServerProc<"icelake-server">; +def : ProcessorModel<"cascadelake", SkylakeServerModel, + ProcessorFeatures.CLXFeatures>; +def : ProcessorModel<"cannonlake", SkylakeServerModel, + ProcessorFeatures.CNLFeatures>; +def : ProcessorModel<"icelake-client", SkylakeServerModel, + ProcessorFeatures.ICLFeatures>; +def : ProcessorModel<"icelake-server", SkylakeServerModel, + ProcessorFeatures.ICXFeatures>; // AMD CPUs. @@ -1143,58 +1181,8 @@ def : Proc<"bdver4", [ FeatureMacroFusion ]>; -// AMD Zen Processors common ISAs -def ZNFeatures : ProcessorFeatures<[], [ - FeatureADX, - FeatureAES, - FeatureAVX2, - FeatureBMI, - FeatureBMI2, - FeatureCLFLUSHOPT, - FeatureCLZERO, - FeatureCMOV, - Feature64Bit, - FeatureCMPXCHG16B, - FeatureF16C, - FeatureFMA, - FeatureFSGSBase, - FeatureFXSR, - FeatureNOPL, - FeatureFastLZCNT, - FeatureLAHFSAHF, - FeatureLZCNT, - FeatureFastBEXTR, - FeatureFast15ByteNOP, - FeatureMacroFusion, - FeatureMMX, - FeatureMOVBE, - FeatureMWAITX, - FeaturePCLMUL, - FeaturePOPCNT, - FeaturePRFCHW, - FeatureRDRAND, - FeatureRDSEED, - FeatureSHA, - FeatureSSE4A, - FeatureSlowSHLD, - FeatureX87, - FeatureXSAVE, - FeatureXSAVEC, - FeatureXSAVEOPT, - FeatureXSAVES]>; - -class Znver1Proc : ProcModel; -def : Znver1Proc<"znver1">; - -class Znver2Proc : ProcModel; -def : Znver2Proc<"znver2">; +def : ProcessorModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures>; +def : ProcessorModel<"znver2", Znver1Model, ProcessorFeatures.ZN2Features>; def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;