From: Sander de Smalen <sander.desmalen@arm.com>
Date: Wed, 27 Mar 2019 17:23:38 +0000 (+0000)
Subject: [AArch64][SVE] Asm: error on unexpected SVE vector register type suffix
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=d0d95f2d77154c8e9993fc2019c3ffc2d36d182c;p=llvm

[AArch64][SVE] Asm: error on unexpected SVE vector register type suffix

This patch fixes an assembler bug that allowed SVE vector registers to contain a
type suffix when not expected. The SVE unpredicated movprfx instruction is the
only instruction affected.

The following are examples of what was previously valid:

    movprfx z0.b, z0.b
    movprfx z0.b, z0.s
    movprfx z0, z0.s

These instructions are now erroneous.

Patch by Cullen Rhodes (c-rhodes)

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D59636


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357094 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 7345ff38edb..6d6c3155ba1 100644
--- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1090,8 +1090,7 @@ public:
     if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
       return DiagnosticPredicateTy::NoMatch;
 
-    if (isSVEVectorReg<Class>() &&
-           (ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
+    if (isSVEVectorReg<Class>() && Reg.ElementWidth == ElementWidth)
       return DiagnosticPredicateTy::Match;
 
     return DiagnosticPredicateTy::NearMatch;
@@ -4442,7 +4441,7 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidZPR64LSL64:
     return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #3'");
   case Match_InvalidZPR0:
-    return Error(Loc, "expected register without element width sufix");
+    return Error(Loc, "expected register without element width suffix");
   case Match_InvalidZPR8:
   case Match_InvalidZPR16:
   case Match_InvalidZPR32:
diff --git a/test/MC/AArch64/SVE/ldr-diagnostics.s b/test/MC/AArch64/SVE/ldr-diagnostics.s
index a881fc17bbd..b025465f6e6 100644
--- a/test/MC/AArch64/SVE/ldr-diagnostics.s
+++ b/test/MC/AArch64/SVE/ldr-diagnostics.s
@@ -22,3 +22,11 @@ ldr z0, [x0, #256, MUL VL]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-256, 255].
 // CHECK-NEXT: ldr z0, [x0, #256, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Unexpected element width suffix
+
+ldr z0.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected register without element width suffix
+// CHECK-NEXT: ldr z0.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/test/MC/AArch64/SVE/movprfx-diagnostics.s b/test/MC/AArch64/SVE/movprfx-diagnostics.s
index 56b1f5cfc72..843e0daebcb 100644
--- a/test/MC/AArch64/SVE/movprfx-diagnostics.s
+++ b/test/MC/AArch64/SVE/movprfx-diagnostics.s
@@ -1,5 +1,24 @@
 // RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve  2>&1 < %s | FileCheck %s
 
+// ------------------------------------------------------------------------- //
+// Type suffix on unpredicated movprfx
+
+movprfx z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movprfx z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.b, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movprfx z0.b, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected register without element width suffix
+// CHECK-NEXT: movprfx z0, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
 // ------------------------------------------------------------------------- //
 // Different destination register (unary)
 
diff --git a/test/MC/AArch64/SVE/str-diagnostics.s b/test/MC/AArch64/SVE/str-diagnostics.s
index d8049981275..f49eb01642f 100644
--- a/test/MC/AArch64/SVE/str-diagnostics.s
+++ b/test/MC/AArch64/SVE/str-diagnostics.s
@@ -22,3 +22,11 @@ str z0, [x0, #256, MUL VL]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-256, 255].
 // CHECK-NEXT: str z0, [x0, #256, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Unexpected element width suffix
+
+str z0.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected register without element width suffix
+// CHECK-NEXT: str z0.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: