From: Alex Bradbury Date: Sat, 30 Mar 2019 05:24:42 +0000 (+0000) Subject: [RISCV][NFC] Remove floating point operations from test/CodeGen/RISCV/vararg.ll X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=d0a191c33cfcff399431d34df5ad8c745ba76652;p=llvm [RISCV][NFC] Remove floating point operations from test/CodeGen/RISCV/vararg.ll This minimises differences in output when compiling with hardware floating point support, which will be done in a future patch (to demonstrate the same vararg calling convention is used). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357339 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/RISCV/vararg.ll b/test/CodeGen/RISCV/vararg.ll index 3de0a230cc6..7c1e48836be 100644 --- a/test/CodeGen/RISCV/vararg.ll +++ b/test/CodeGen/RISCV/vararg.ll @@ -214,7 +214,7 @@ define void @va1_caller() nounwind { ; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned" ; register pair (where the first register is even-numbered). -define double @va2(i8 *%fmt, ...) nounwind { +define i64 @va2(i8 *%fmt, ...) nounwind { ; RV32I-FPELIM-LABEL: va2: ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -48 @@ -271,11 +271,12 @@ define double @va2(i8 *%fmt, ...) nounwind { store i8* %argp.next, i8** %va, align 4 %5 = inttoptr i32 %4 to double* %6 = load double, double* %5, align 8 + %7 = bitcast double %6 to i64 call void @llvm.va_end(i8* %1) - ret double %6 + ret i64 %7 } -define double @va2_va_arg(i8 *%fmt, ...) nounwind { +define i64 @va2_va_arg(i8 *%fmt, ...) nounwind { ; RV32I-FPELIM-LABEL: va2_va_arg: ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -48 @@ -327,7 +328,8 @@ define double @va2_va_arg(i8 *%fmt, ...) nounwind { call void @llvm.va_start(i8* %1) %2 = va_arg i8** %va, double call void @llvm.va_end(i8* %1) - ret double %2 + %3 = bitcast double %2 to i64 + ret i64 %3 } define void @va2_caller() nounwind { @@ -355,35 +357,33 @@ define void @va2_caller() nounwind { ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: ret - %1 = call double (i8*, ...) @va2(i8* undef, double 1.000000e+00) + %1 = call i64 (i8*, ...) @va2(i8* undef, double 1.000000e+00) ret void } -; Ensure a named double argument is passed in a1 and a2, while the vararg -; double is passed in a4 and a5 (rather than a3 and a4) +; On RV32, Ensure a named 2*xlen argument is passed in a1 and a2, while the +; vararg double is passed in a4 and a5 (rather than a3 and a4) -define double @va3(i32 %a, double %b, ...) nounwind { +define i64 @va3(i32 %a, i64 %b, ...) nounwind { ; RV32I-FPELIM-LABEL: va3: ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -32 -; RV32I-FPELIM-NEXT: sw ra, 4(sp) -; RV32I-FPELIM-NEXT: mv t0, a2 -; RV32I-FPELIM-NEXT: mv a0, a1 ; RV32I-FPELIM-NEXT: sw a7, 28(sp) ; RV32I-FPELIM-NEXT: sw a6, 24(sp) ; RV32I-FPELIM-NEXT: sw a5, 20(sp) ; RV32I-FPELIM-NEXT: sw a4, 16(sp) ; RV32I-FPELIM-NEXT: sw a3, 12(sp) -; RV32I-FPELIM-NEXT: addi a1, sp, 27 -; RV32I-FPELIM-NEXT: sw a1, 0(sp) -; RV32I-FPELIM-NEXT: addi a1, sp, 19 -; RV32I-FPELIM-NEXT: andi a1, a1, -8 -; RV32I-FPELIM-NEXT: lw a2, 0(a1) -; RV32I-FPELIM-NEXT: ori a1, a1, 4 -; RV32I-FPELIM-NEXT: lw a3, 0(a1) -; RV32I-FPELIM-NEXT: mv a1, t0 -; RV32I-FPELIM-NEXT: call __adddf3 -; RV32I-FPELIM-NEXT: lw ra, 4(sp) +; RV32I-FPELIM-NEXT: addi a0, sp, 27 +; RV32I-FPELIM-NEXT: sw a0, 4(sp) +; RV32I-FPELIM-NEXT: addi a0, sp, 19 +; RV32I-FPELIM-NEXT: andi a0, a0, -8 +; RV32I-FPELIM-NEXT: ori a3, a0, 4 +; RV32I-FPELIM-NEXT: lw a3, 0(a3) +; RV32I-FPELIM-NEXT: add a2, a2, a3 +; RV32I-FPELIM-NEXT: lw a0, 0(a0) +; RV32I-FPELIM-NEXT: add a0, a1, a0 +; RV32I-FPELIM-NEXT: sltu a1, a0, a1 +; RV32I-FPELIM-NEXT: add a1, a2, a1 ; RV32I-FPELIM-NEXT: addi sp, sp, 32 ; RV32I-FPELIM-NEXT: ret ; @@ -393,22 +393,22 @@ define double @va3(i32 %a, double %b, ...) nounwind { ; RV32I-WITHFP-NEXT: sw ra, 20(sp) ; RV32I-WITHFP-NEXT: sw s0, 16(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 24 -; RV32I-WITHFP-NEXT: mv t0, a2 -; RV32I-WITHFP-NEXT: mv a0, a1 ; RV32I-WITHFP-NEXT: sw a7, 20(s0) ; RV32I-WITHFP-NEXT: sw a6, 16(s0) ; RV32I-WITHFP-NEXT: sw a5, 12(s0) ; RV32I-WITHFP-NEXT: sw a4, 8(s0) ; RV32I-WITHFP-NEXT: sw a3, 4(s0) -; RV32I-WITHFP-NEXT: addi a1, s0, 19 -; RV32I-WITHFP-NEXT: sw a1, -12(s0) -; RV32I-WITHFP-NEXT: addi a1, s0, 11 -; RV32I-WITHFP-NEXT: andi a1, a1, -8 -; RV32I-WITHFP-NEXT: lw a2, 0(a1) -; RV32I-WITHFP-NEXT: ori a1, a1, 4 -; RV32I-WITHFP-NEXT: lw a3, 0(a1) -; RV32I-WITHFP-NEXT: mv a1, t0 -; RV32I-WITHFP-NEXT: call __adddf3 +; RV32I-WITHFP-NEXT: addi a0, s0, 19 +; RV32I-WITHFP-NEXT: sw a0, -12(s0) +; RV32I-WITHFP-NEXT: addi a0, s0, 11 +; RV32I-WITHFP-NEXT: andi a0, a0, -8 +; RV32I-WITHFP-NEXT: ori a3, a0, 4 +; RV32I-WITHFP-NEXT: lw a3, 0(a3) +; RV32I-WITHFP-NEXT: add a2, a2, a3 +; RV32I-WITHFP-NEXT: lw a0, 0(a0) +; RV32I-WITHFP-NEXT: add a0, a1, a0 +; RV32I-WITHFP-NEXT: sltu a1, a0, a1 +; RV32I-WITHFP-NEXT: add a1, a2, a1 ; RV32I-WITHFP-NEXT: lw s0, 16(sp) ; RV32I-WITHFP-NEXT: lw ra, 20(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 48 @@ -426,33 +426,32 @@ define double @va3(i32 %a, double %b, ...) nounwind { %5 = inttoptr i32 %4 to double* %6 = load double, double* %5, align 8 call void @llvm.va_end(i8* %1) - %7 = fadd double %b, %6 - ret double %7 + %7 = bitcast double %6 to i64 + %8 = add i64 %b, %7 + ret i64 %8 } -define double @va3_va_arg(i32 %a, double %b, ...) nounwind { +define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind { ; RV32I-FPELIM-LABEL: va3_va_arg: ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -32 -; RV32I-FPELIM-NEXT: sw ra, 4(sp) -; RV32I-FPELIM-NEXT: mv t0, a2 -; RV32I-FPELIM-NEXT: mv a0, a1 ; RV32I-FPELIM-NEXT: sw a7, 28(sp) ; RV32I-FPELIM-NEXT: sw a6, 24(sp) ; RV32I-FPELIM-NEXT: sw a5, 20(sp) ; RV32I-FPELIM-NEXT: sw a4, 16(sp) ; RV32I-FPELIM-NEXT: sw a3, 12(sp) -; RV32I-FPELIM-NEXT: addi a1, sp, 19 -; RV32I-FPELIM-NEXT: andi a1, a1, -8 -; RV32I-FPELIM-NEXT: ori a3, a1, 4 -; RV32I-FPELIM-NEXT: sw a3, 0(sp) -; RV32I-FPELIM-NEXT: lw a2, 0(a1) -; RV32I-FPELIM-NEXT: addi a1, a3, 4 -; RV32I-FPELIM-NEXT: sw a1, 0(sp) +; RV32I-FPELIM-NEXT: addi a0, sp, 19 +; RV32I-FPELIM-NEXT: andi a0, a0, -8 +; RV32I-FPELIM-NEXT: ori a3, a0, 4 +; RV32I-FPELIM-NEXT: sw a3, 4(sp) +; RV32I-FPELIM-NEXT: lw a0, 0(a0) +; RV32I-FPELIM-NEXT: addi a4, a3, 4 +; RV32I-FPELIM-NEXT: sw a4, 4(sp) ; RV32I-FPELIM-NEXT: lw a3, 0(a3) -; RV32I-FPELIM-NEXT: mv a1, t0 -; RV32I-FPELIM-NEXT: call __adddf3 -; RV32I-FPELIM-NEXT: lw ra, 4(sp) +; RV32I-FPELIM-NEXT: add a2, a2, a3 +; RV32I-FPELIM-NEXT: add a0, a1, a0 +; RV32I-FPELIM-NEXT: sltu a1, a0, a1 +; RV32I-FPELIM-NEXT: add a1, a2, a1 ; RV32I-FPELIM-NEXT: addi sp, sp, 32 ; RV32I-FPELIM-NEXT: ret ; @@ -462,23 +461,23 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind { ; RV32I-WITHFP-NEXT: sw ra, 20(sp) ; RV32I-WITHFP-NEXT: sw s0, 16(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 24 -; RV32I-WITHFP-NEXT: mv t0, a2 -; RV32I-WITHFP-NEXT: mv a0, a1 ; RV32I-WITHFP-NEXT: sw a7, 20(s0) ; RV32I-WITHFP-NEXT: sw a6, 16(s0) ; RV32I-WITHFP-NEXT: sw a5, 12(s0) ; RV32I-WITHFP-NEXT: sw a4, 8(s0) ; RV32I-WITHFP-NEXT: sw a3, 4(s0) -; RV32I-WITHFP-NEXT: addi a1, s0, 11 -; RV32I-WITHFP-NEXT: andi a1, a1, -8 -; RV32I-WITHFP-NEXT: ori a3, a1, 4 +; RV32I-WITHFP-NEXT: addi a0, s0, 11 +; RV32I-WITHFP-NEXT: andi a0, a0, -8 +; RV32I-WITHFP-NEXT: ori a3, a0, 4 ; RV32I-WITHFP-NEXT: sw a3, -12(s0) -; RV32I-WITHFP-NEXT: lw a2, 0(a1) -; RV32I-WITHFP-NEXT: addi a1, a3, 4 -; RV32I-WITHFP-NEXT: sw a1, -12(s0) +; RV32I-WITHFP-NEXT: lw a0, 0(a0) +; RV32I-WITHFP-NEXT: addi a4, a3, 4 +; RV32I-WITHFP-NEXT: sw a4, -12(s0) ; RV32I-WITHFP-NEXT: lw a3, 0(a3) -; RV32I-WITHFP-NEXT: mv a1, t0 -; RV32I-WITHFP-NEXT: call __adddf3 +; RV32I-WITHFP-NEXT: add a2, a2, a3 +; RV32I-WITHFP-NEXT: add a0, a1, a0 +; RV32I-WITHFP-NEXT: sltu a1, a0, a1 +; RV32I-WITHFP-NEXT: add a1, a2, a1 ; RV32I-WITHFP-NEXT: lw s0, 16(sp) ; RV32I-WITHFP-NEXT: lw ra, 20(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 48 @@ -488,8 +487,9 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind { call void @llvm.va_start(i8* %1) %2 = va_arg i8** %va, double call void @llvm.va_end(i8* %1) - %3 = fadd double %b, %2 - ret double %3 + %3 = bitcast double %2 to i64 + %4 = add i64 %b, %3 + ret i64 %4 } define void @va3_caller() nounwind { @@ -498,8 +498,8 @@ define void @va3_caller() nounwind { ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: addi a0, zero, 2 -; RV32I-FPELIM-NEXT: mv a1, zero -; RV32I-FPELIM-NEXT: lui a2, 261888 +; RV32I-FPELIM-NEXT: addi a1, zero, 1111 +; RV32I-FPELIM-NEXT: mv a2, zero ; RV32I-FPELIM-NEXT: mv a4, zero ; RV32I-FPELIM-NEXT: lui a5, 262144 ; RV32I-FPELIM-NEXT: call va3 @@ -514,8 +514,8 @@ define void @va3_caller() nounwind { ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi a0, zero, 2 -; RV32I-WITHFP-NEXT: mv a1, zero -; RV32I-WITHFP-NEXT: lui a2, 261888 +; RV32I-WITHFP-NEXT: addi a1, zero, 1111 +; RV32I-WITHFP-NEXT: mv a2, zero ; RV32I-WITHFP-NEXT: mv a4, zero ; RV32I-WITHFP-NEXT: lui a5, 262144 ; RV32I-WITHFP-NEXT: call va3 @@ -523,7 +523,7 @@ define void @va3_caller() nounwind { ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: ret - %1 = call double (i32, double, ...) @va3(i32 2, double 1.000000e+00, double 2.000000e+00) + %1 = call i64 (i32, i64, ...) @va3(i32 2, i64 1111, double 2.000000e+00) ret void }