From: Mark Lacey <mark.lacey@apple.com>
Date: Wed, 31 Jul 2019 20:34:02 +0000 (+0000)
Subject: [GISel] Pass MD_callees metadata down in call lowering.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=cf29ef1a9955c4111c92090b59cd6006d84ff5dc;p=llvm
[GISel] Pass MD_callees metadata down in call lowering.
Summary:
This will make it possible to improve IPRA by taking into account
register usage in indirect calls.
NFC yet; this is just laying the groundwork to start building
up patches to take advantage of the information for improved register
allocation.
Reviewers: aditya_nandakumar, volkan, qcolombet, arsenm, rovka, aemerson, paquette
Subscribers: sdardis, wdng, javed.absar, hiraditya, jrtc27, atanasyan, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367476 91177308-0d34-0410-b5e6-96231b3b80d8
---
diff --git a/include/llvm/CodeGen/GlobalISel/CallLowering.h b/include/llvm/CodeGen/GlobalISel/CallLowering.h
index d717121ad78..b5e23c31d36 100644
--- a/include/llvm/CodeGen/GlobalISel/CallLowering.h
+++ b/include/llvm/CodeGen/GlobalISel/CallLowering.h
@@ -240,11 +240,12 @@ public:
/// \return true if the lowering succeeded, false otherwise.
virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
- ArrayRef<ArgInfo> OrigArgs,
- Register SwiftErrorVReg) const {
+ ArrayRef<ArgInfo> OrigArgs, Register SwiftErrorVReg,
+ const MDNode *KnownCallees = nullptr) const {
if (!supportSwiftError()) {
assert(SwiftErrorVReg == 0 && "trying to use unsupported swifterror");
- return lowerCall(MIRBuilder, CallConv, Callee, OrigRet, OrigArgs);
+ return lowerCall(MIRBuilder, CallConv, Callee, OrigRet, OrigArgs,
+ KnownCallees);
}
return false;
}
@@ -253,7 +254,8 @@ public:
/// do not support swifterror value promotion.
virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
- ArrayRef<ArgInfo> OrigArgs) const {
+ ArrayRef<ArgInfo> OrigArgs,
+ const MDNode *KnownCallees = nullptr) const {
return false;
}
diff --git a/lib/CodeGen/GlobalISel/CallLowering.cpp b/lib/CodeGen/GlobalISel/CallLowering.cpp
index a5d8205a34a..9f950131c85 100644
--- a/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Instructions.h"
+#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Module.h"
#define DEBUG_TYPE "call-lowering"
@@ -61,8 +62,11 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,
if (!OrigRet.Ty->isVoidTy())
setArgFlags(OrigRet, AttributeList::ReturnIndex, DL, CS);
+ const MDNode *KnownCallees =
+ CS.getInstruction()->getMetadata(LLVMContext::MD_callees);
+
return lowerCall(MIRBuilder, CS.getCallingConv(), Callee, OrigRet, OrigArgs,
- SwiftErrorVReg);
+ SwiftErrorVReg, KnownCallees);
}
template <typename FuncInfoTy>
diff --git a/lib/Target/AArch64/AArch64CallLowering.cpp b/lib/Target/AArch64/AArch64CallLowering.cpp
index 59757769c89..fb9b5ab7e85 100644
--- a/lib/Target/AArch64/AArch64CallLowering.cpp
+++ b/lib/Target/AArch64/AArch64CallLowering.cpp
@@ -406,7 +406,8 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const MachineOperand &Callee,
const ArgInfo &OrigRet,
ArrayRef<ArgInfo> OrigArgs,
- Register SwiftErrorVReg) const {
+ Register SwiftErrorVReg,
+ const MDNode *KnownCallees) const {
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = MF.getFunction();
MachineRegisterInfo &MRI = MF.getRegInfo();
diff --git a/lib/Target/AArch64/AArch64CallLowering.h b/lib/Target/AArch64/AArch64CallLowering.h
index 4f428f25453..2446d980bcf 100644
--- a/lib/Target/AArch64/AArch64CallLowering.h
+++ b/lib/Target/AArch64/AArch64CallLowering.h
@@ -42,13 +42,15 @@ public:
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
- ArrayRef<ArgInfo> OrigArgs,
- Register SwiftErrorVReg) const override;
+ ArrayRef<ArgInfo> OrigArgs, Register SwiftErrorVReg,
+ const MDNode *KnownCallees) const override;
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
- ArrayRef<ArgInfo> OrigArgs) const override {
- return lowerCall(MIRBuilder, CallConv, Callee, OrigRet, OrigArgs, 0);
+ ArrayRef<ArgInfo> OrigArgs,
+ const MDNode *KnownCallees) const override {
+ return lowerCall(MIRBuilder, CallConv, Callee, OrigRet, OrigArgs, 0,
+ KnownCallees);
}
bool supportSwiftError() const override { return true; }
diff --git a/lib/Target/ARM/ARMCallLowering.cpp b/lib/Target/ARM/ARMCallLowering.cpp
index 0cbe6e1871e..790998b8c65 100644
--- a/lib/Target/ARM/ARMCallLowering.cpp
+++ b/lib/Target/ARM/ARMCallLowering.cpp
@@ -502,7 +502,8 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
CallingConv::ID CallConv,
const MachineOperand &Callee,
const ArgInfo &OrigRet,
- ArrayRef<ArgInfo> OrigArgs) const {
+ ArrayRef<ArgInfo> OrigArgs,
+ const MDNode *KnownCallees) const {
MachineFunction &MF = MIRBuilder.getMF();
const auto &TLI = *getTLI<ARMTargetLowering>();
const auto &DL = MF.getDataLayout();
diff --git a/lib/Target/ARM/ARMCallLowering.h b/lib/Target/ARM/ARMCallLowering.h
index 794127b5ebc..e0f1e3dfd70 100644
--- a/lib/Target/ARM/ARMCallLowering.h
+++ b/lib/Target/ARM/ARMCallLowering.h
@@ -40,7 +40,8 @@ public:
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
- ArrayRef<ArgInfo> OrigArgs) const override;
+ ArrayRef<ArgInfo> OrigArgs,
+ const MDNode *KnownCallees) const override;
private:
bool lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val,
diff --git a/lib/Target/Mips/MipsCallLowering.cpp b/lib/Target/Mips/MipsCallLowering.cpp
index ec24a65b803..849f9558ac2 100644
--- a/lib/Target/Mips/MipsCallLowering.cpp
+++ b/lib/Target/Mips/MipsCallLowering.cpp
@@ -502,7 +502,8 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
CallingConv::ID CallConv,
const MachineOperand &Callee,
const ArgInfo &OrigRet,
- ArrayRef<ArgInfo> OrigArgs) const {
+ ArrayRef<ArgInfo> OrigArgs,
+ const MDNode *KnownCallees) const {
if (CallConv != CallingConv::C)
return false;
diff --git a/lib/Target/Mips/MipsCallLowering.h b/lib/Target/Mips/MipsCallLowering.h
index 11c2d53ad35..1245fcb5795 100644
--- a/lib/Target/Mips/MipsCallLowering.h
+++ b/lib/Target/Mips/MipsCallLowering.h
@@ -70,7 +70,8 @@ public:
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
- ArrayRef<ArgInfo> OrigArgs) const override;
+ ArrayRef<ArgInfo> OrigArgs,
+ const MDNode *KnownCallees) const override;
private:
/// Based on registers available on target machine split or extend
diff --git a/lib/Target/X86/X86CallLowering.cpp b/lib/Target/X86/X86CallLowering.cpp
index b16b3839c85..e97a28a760c 100644
--- a/lib/Target/X86/X86CallLowering.cpp
+++ b/lib/Target/X86/X86CallLowering.cpp
@@ -375,7 +375,8 @@ bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
CallingConv::ID CallConv,
const MachineOperand &Callee,
const ArgInfo &OrigRet,
- ArrayRef<ArgInfo> OrigArgs) const {
+ ArrayRef<ArgInfo> OrigArgs,
+ const MDNode *KnownCallees) const {
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = MF.getFunction();
MachineRegisterInfo &MRI = MF.getRegInfo();
diff --git a/lib/Target/X86/X86CallLowering.h b/lib/Target/X86/X86CallLowering.h
index 0445331bc3f..97d12e8c740 100644
--- a/lib/Target/X86/X86CallLowering.h
+++ b/lib/Target/X86/X86CallLowering.h
@@ -36,7 +36,8 @@ public:
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
- ArrayRef<ArgInfo> OrigArgs) const override;
+ ArrayRef<ArgInfo> OrigArgs,
+ const MDNode *KnownCallees) const override;
private:
/// A function of this type is used to perform value split action.