From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 2 Jul 2019 14:49:29 +0000 (+0000)
Subject: GlobalISel: Define GINodeEquiv for G_UMULH/G_SMULH
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=ce64e4118fc9c7e0d64dad814bc3b63325d6c754;p=llvm

GlobalISel: Define GINodeEquiv for G_UMULH/G_SMULH

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364931 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index 35c80c2a5a3..6cc58d6521d 100644
--- a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -49,6 +49,8 @@ def : GINodeEquiv<G_FCONSTANT, fpimm>;
 def : GINodeEquiv<G_ADD, add>;
 def : GINodeEquiv<G_SUB, sub>;
 def : GINodeEquiv<G_MUL, mul>;
+def : GINodeEquiv<G_UMULH, mulhu>;
+def : GINodeEquiv<G_SMULH, mulhs>;
 def : GINodeEquiv<G_SDIV, sdiv>;
 def : GINodeEquiv<G_UDIV, udiv>;
 def : GINodeEquiv<G_SREM, srem>;
diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
new file mode 100644
index 00000000000..4d412681597
--- /dev/null
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
@@ -0,0 +1,85 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s
+# RUN: FileCheck -check-prefix=ERR  %s < %t
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s
+# RUN: FileCheck -check-prefix=ERR  %s < %t
+
+# ERR-NOT: remark:
+# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_SMULH %0:sgpr, %1:sgpr (in function: smulh_s32_ss)
+# ERR-NOT: remark:
+
+---
+name: smulh_s32_ss
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; GCN-LABEL: name: smulh_s32_ss
+    ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; GCN: [[SMULH:%[0-9]+]]:sgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
+    ; GCN: S_ENDPGM 0, implicit [[SMULH]](s32)
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s32) = G_SMULH %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+name: smulh_s32_sv
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $vgpr0
+    ; GCN-LABEL: name: smulh_s32_sv
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[V_MUL_HI_I32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32 [[COPY]], [[COPY1]], implicit $exec
+    ; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_I32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:vgpr(s32) = COPY $vgpr0
+    %2:vgpr(s32) = G_SMULH %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+name: smulh_s32_vs
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $vgpr0
+    ; GCN-LABEL: name: smulh_s32_vs
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: [[V_MUL_HI_I32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32 [[COPY]], [[COPY1]], implicit $exec
+    ; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_I32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:sgpr(s32) = COPY $sgpr0
+    %2:vgpr(s32) = G_SMULH %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+name: smulh_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; GCN-LABEL: name: smulh_s32_vv
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; GCN: [[V_MUL_HI_I32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32 [[COPY]], [[COPY1]], implicit $exec
+    ; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_I32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s32) = G_SMULH %0, %1
+    S_ENDPGM 0, implicit %2
+...
diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
new file mode 100644
index 00000000000..a4726fcf6c7
--- /dev/null
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
@@ -0,0 +1,85 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s
+# RUN: FileCheck -check-prefix=ERR  %s < %t
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s
+# RUN: FileCheck -check-prefix=ERR  %s < %t
+
+# ERR-NOT: remark:
+# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_UMULH %0:sgpr, %1:sgpr (in function: umulh_s32_ss)
+# ERR-NOT: remark:
+
+---
+name: umulh_s32_ss
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; GCN-LABEL: name: umulh_s32_ss
+    ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; GCN: [[UMULH:%[0-9]+]]:sgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
+    ; GCN: S_ENDPGM 0, implicit [[UMULH]](s32)
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s32) = G_UMULH %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+name: umulh_s32_sv
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $vgpr0
+    ; GCN-LABEL: name: umulh_s32_sv
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[V_MUL_HI_U32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32 [[COPY]], [[COPY1]], implicit $exec
+    ; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_U32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:vgpr(s32) = COPY $vgpr0
+    %2:vgpr(s32) = G_UMULH %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+name: umulh_s32_vs
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $vgpr0
+    ; GCN-LABEL: name: umulh_s32_vs
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: [[V_MUL_HI_U32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32 [[COPY]], [[COPY1]], implicit $exec
+    ; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_U32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:sgpr(s32) = COPY $sgpr0
+    %2:vgpr(s32) = G_UMULH %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+name: umulh_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; GCN-LABEL: name: umulh_s32_vv
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; GCN: [[V_MUL_HI_U32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32 [[COPY]], [[COPY1]], implicit $exec
+    ; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_U32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s32) = G_UMULH %0, %1
+    S_ENDPGM 0, implicit %2
+...