From: Matt Arsenault Date: Fri, 28 Jun 2019 01:47:44 +0000 (+0000) Subject: GlobalISel: Use Register X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=cc1390c334d8de333d2a32151a7c939d272a6f99;p=llvm GlobalISel: Use Register git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364618 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/CodeGen/GlobalISel/RegBankSelect.h b/include/llvm/CodeGen/GlobalISel/RegBankSelect.h index e704ce44779..d9d076ba312 100644 --- a/include/llvm/CodeGen/GlobalISel/RegBankSelect.h +++ b/include/llvm/CodeGen/GlobalISel/RegBankSelect.h @@ -523,7 +523,7 @@ private: /// \p OnlyAssign == true means that \p Reg just needs to be assigned a /// register bank. I.e., no repairing is necessary to have the /// assignment match. - bool assignmentMatch(unsigned Reg, + bool assignmentMatch(Register Reg, const RegisterBankInfo::ValueMapping &ValMapping, bool &OnlyAssign) const; @@ -562,7 +562,7 @@ private: bool repairReg(MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping, RegBankSelect::RepairingPlacement &RepairPt, - const iterator_range::const_iterator> + const iterator_range::const_iterator> &NewVRegs); /// Return the cost of the instruction needed to map \p MO to \p ValMapping. diff --git a/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h index 518719e7774..e84b1c3ea8b 100644 --- a/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h +++ b/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h @@ -18,6 +18,7 @@ #include "llvm/ADT/Hashing.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/iterator_range.h" +#include "llvm/CodeGen/Register.h" #include "llvm/Support/ErrorHandling.h" #include #include @@ -281,7 +282,7 @@ public: SmallVector OpToNewVRegIdx; /// Hold the registers that will be used to map MI with InstrMapping. - SmallVector NewVRegs; + SmallVector NewVRegs; /// Current MachineRegisterInfo, used to create new virtual registers. MachineRegisterInfo &MRI; @@ -302,15 +303,15 @@ public: /// \return The iterator range for the space created. // /// \pre getMI().getOperand(OpIdx).isReg() - iterator_range::iterator> + iterator_range::iterator> getVRegsMem(unsigned OpIdx); /// Get the end iterator for a range starting at \p StartIdx and /// spannig \p NumVal in NewVRegs. /// \pre StartIdx + NumVal <= NewVRegs.size() - SmallVectorImpl::const_iterator + SmallVectorImpl::const_iterator getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const; - SmallVectorImpl::iterator getNewVRegsEnd(unsigned StartIdx, + SmallVectorImpl::iterator getNewVRegsEnd(unsigned StartIdx, unsigned NumVal); public: @@ -356,7 +357,7 @@ public: /// /// \post the \p PartialMapIdx-th register of the value mapping of the \p /// OpIdx-th operand has been set. - void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg); + void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg); /// Get all the virtual registers required to map the \p OpIdx-th operand of /// the instruction. @@ -370,7 +371,7 @@ public: /// /// \pre getMI().getOperand(OpIdx).isReg() /// \pre ForDebug || All partial mappings have been set a register - iterator_range::const_iterator> + iterator_range::const_iterator> getVRegs(unsigned OpIdx, bool ForDebug = false) const; /// Print this operands mapper on dbgs() stream. @@ -434,7 +435,7 @@ protected: /// Get the MinimalPhysRegClass for Reg. /// \pre Reg is a physical register. const TargetRegisterClass & - getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const; + getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const; /// Try to get the mapping of \p MI. /// See getInstrMapping for more details on what a mapping represents. @@ -579,7 +580,7 @@ public: /// or a register bank, then this returns nullptr. /// /// \pre Reg != 0 (NoRegister) - const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, + const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const; /// Get the total number of register banks. @@ -640,7 +641,7 @@ public: /// \note Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel /// purpose, including non-select passes of GlobalISel static const TargetRegisterClass * - constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, + constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI); /// Identifier used when the related instruction mapping instance @@ -725,7 +726,7 @@ public: /// virtual register. /// /// \pre \p Reg != 0 (NoRegister). - unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, + unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const; /// Check that information hold by this instance make sense for the diff --git a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 62bfa4f3766..adc0eb5c166 100644 --- a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -190,12 +190,12 @@ void LegalizerHelper::insertParts(Register DstReg, unsigned PartSize = PartTy.getSizeInBits(); unsigned LeftoverPartSize = LeftoverTy.getSizeInBits(); - unsigned CurResultReg = MRI.createGenericVirtualRegister(ResultTy); + Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy); MIRBuilder.buildUndef(CurResultReg); unsigned Offset = 0; - for (unsigned PartReg : PartRegs) { - unsigned NewResultReg = MRI.createGenericVirtualRegister(ResultTy); + for (Register PartReg : PartRegs) { + Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy); MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset); CurResultReg = NewResultReg; Offset += PartSize; @@ -203,7 +203,7 @@ void LegalizerHelper::insertParts(Register DstReg, for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) { // Use the original output register for the final insert to avoid a copy. - unsigned NewResultReg = (I + 1 == E) ? + Register NewResultReg = (I + 1 == E) ? DstReg : MRI.createGenericVirtualRegister(ResultTy); MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset); @@ -474,7 +474,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, DstRegs.push_back( MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg()); - unsigned DstReg = MI.getOperand(0).getReg(); + Register DstReg = MI.getOperand(0).getReg(); if(MRI.getType(DstReg).isVector()) MIRBuilder.buildBuildVector(DstReg, DstRegs); else @@ -764,7 +764,7 @@ void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, SmallVector Parts; Parts.push_back(MO.getReg()); - unsigned ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); + Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); for (unsigned I = 1; I != NumParts; ++I) Parts.push_back(ImpDef); @@ -1649,7 +1649,7 @@ LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx, const unsigned Opc = MI.getOpcode(); const unsigned NumOps = MI.getNumOperands() - 1; const unsigned NarrowSize = NarrowTy.getSizeInBits(); - const unsigned DstReg = MI.getOperand(0).getReg(); + const Register DstReg = MI.getOperand(0).getReg(); const unsigned Flags = MI.getFlags(); const LLT DstTy = MRI.getType(DstReg); const unsigned Size = DstTy.getSizeInBits(); diff --git a/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/lib/CodeGen/GlobalISel/RegBankSelect.cpp index 6a561392d8b..42be88fcf94 100644 --- a/lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ b/lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -108,7 +108,7 @@ void RegBankSelect::getAnalysisUsage(AnalysisUsage &AU) const { } bool RegBankSelect::assignmentMatch( - unsigned Reg, const RegisterBankInfo::ValueMapping &ValMapping, + Register Reg, const RegisterBankInfo::ValueMapping &ValMapping, bool &OnlyAssign) const { // By default we assume we will have to repair something. OnlyAssign = false; @@ -133,7 +133,7 @@ bool RegBankSelect::assignmentMatch( bool RegBankSelect::repairReg( MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping, RegBankSelect::RepairingPlacement &RepairPt, - const iterator_range::const_iterator> &NewVRegs) { + const iterator_range::const_iterator> &NewVRegs) { assert(ValMapping.NumBreakDowns == (unsigned)size(NewVRegs) && "need new vreg for each breakdown"); @@ -145,8 +145,8 @@ bool RegBankSelect::repairReg( if (ValMapping.NumBreakDowns == 1) { // Assume we are repairing a use and thus, the original reg will be // the source of the repairing. - unsigned Src = MO.getReg(); - unsigned Dst = *NewVRegs.begin(); + Register Src = MO.getReg(); + Register Dst = *NewVRegs.begin(); // If we repair a definition, swap the source and destination for // the repairing. @@ -193,14 +193,14 @@ bool RegBankSelect::repairReg( MIRBuilder.buildInstrNoInsert(MergeOp) .addDef(MO.getReg()); - for (unsigned SrcReg : NewVRegs) + for (Register SrcReg : NewVRegs) MergeBuilder.addUse(SrcReg); MI = MergeBuilder; } else { MachineInstrBuilder UnMergeBuilder = MIRBuilder.buildInstrNoInsert(TargetOpcode::G_UNMERGE_VALUES); - for (unsigned DefReg : NewVRegs) + for (Register DefReg : NewVRegs) UnMergeBuilder.addDef(DefReg); UnMergeBuilder.addUse(MO.getReg()); @@ -397,7 +397,7 @@ void RegBankSelect::tryAvoidingSplit( // repairing. // Check if this is a physical or virtual register. - unsigned Reg = MO.getReg(); + Register Reg = MO.getReg(); if (TargetRegisterInfo::isPhysicalRegister(Reg)) { // We are going to split every outgoing edges. // Check that this is possible. @@ -468,7 +468,7 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping( const MachineOperand &MO = MI.getOperand(OpIdx); if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); + Register Reg = MO.getReg(); if (!Reg) continue; LLVM_DEBUG(dbgs() << "Opd" << OpIdx << '\n'); @@ -594,7 +594,7 @@ bool RegBankSelect::applyMapping( MachineOperand &MO = MI.getOperand(OpIdx); const RegisterBankInfo::ValueMapping &ValMapping = InstrMapping.getOperandMapping(OpIdx); - unsigned Reg = MO.getReg(); + Register Reg = MO.getReg(); switch (RepairPt.getKind()) { case RepairingPlacement::Reassign: @@ -757,7 +757,7 @@ RegBankSelect::RepairingPlacement::RepairingPlacement( MachineBasicBlock &Pred = *MI.getOperand(OpIdx + 1).getMBB(); // Check if we can move the insertion point prior to the // terminators of the predecessor. - unsigned Reg = MO.getReg(); + Register Reg = MO.getReg(); MachineBasicBlock::iterator It = Pred.getLastNonDebugInstr(); for (auto Begin = Pred.begin(); It != Begin && It->isTerminator(); --It) if (It->modifiesRegister(Reg, &TRI)) { diff --git a/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index 46f1bc5bae1..159422e3887 100644 --- a/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -80,7 +80,7 @@ bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const { } const RegisterBank * -RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, +RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const { if (TargetRegisterInfo::isPhysicalRegister(Reg)) return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI)); @@ -95,7 +95,7 @@ RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, } const TargetRegisterClass & -RegisterBankInfo::getMinimalPhysRegClass(unsigned Reg, +RegisterBankInfo::getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const { assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Reg must be a physreg"); @@ -125,7 +125,7 @@ const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( } const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister( - unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) { + Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) { // If the register already has a class, fallback to MRI::constrainRegClass. auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg); @@ -180,7 +180,7 @@ RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const { const MachineOperand &MO = MI.getOperand(OpIdx); if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); + Register Reg = MO.getReg(); if (!Reg) continue; // The register bank of Reg is just a side effect of the current @@ -229,7 +229,7 @@ RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const { const MachineOperand &MO = MI.getOperand(OpIdx); if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); + Register Reg = MO.getReg(); if (!Reg) continue; @@ -454,14 +454,14 @@ void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) { assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns == 1 && "This mapping is too complex for this function"); - iterator_range::const_iterator> NewRegs = + iterator_range::const_iterator> NewRegs = OpdMapper.getVRegs(OpIdx); if (empty(NewRegs)) { LLVM_DEBUG(dbgs() << " has not been repaired, nothing to be done\n"); continue; } - unsigned OrigReg = MO.getReg(); - unsigned NewReg = *NewRegs.begin(); + Register OrigReg = MO.getReg(); + Register NewReg = *NewRegs.begin(); LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); MO.setReg(NewReg); LLVM_DEBUG(dbgs() << " with " << printReg(NewReg, nullptr)); @@ -486,7 +486,7 @@ void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) { } } -unsigned RegisterBankInfo::getSizeInBits(unsigned Reg, +unsigned RegisterBankInfo::getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const { if (TargetRegisterInfo::isPhysicalRegister(Reg)) { @@ -608,7 +608,7 @@ bool RegisterBankInfo::InstructionMapping::verify( "We should not care about non-reg mapping"); continue; } - unsigned Reg = MO.getReg(); + Register Reg = MO.getReg(); if (!Reg) continue; assert(getOperandMapping(Idx).isValid() && @@ -653,7 +653,7 @@ RegisterBankInfo::OperandsMapper::OperandsMapper( assert(InstrMapping.verify(MI) && "Invalid mapping for MI"); } -iterator_range::iterator> +iterator_range::iterator> RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) { assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access"); unsigned NumPartialVal = @@ -669,18 +669,18 @@ RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) { for (unsigned i = 0; i < NumPartialVal; ++i) NewVRegs.push_back(0); } - SmallVectorImpl::iterator End = + SmallVectorImpl::iterator End = getNewVRegsEnd(StartIdx, NumPartialVal); return make_range(&NewVRegs[StartIdx], End); } -SmallVectorImpl::const_iterator +SmallVectorImpl::const_iterator RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const { return const_cast(this)->getNewVRegsEnd(StartIdx, NumVal); } -SmallVectorImpl::iterator +SmallVectorImpl::iterator RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) { assert((NewVRegs.size() == StartIdx + NumVal || @@ -692,11 +692,11 @@ RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx, void RegisterBankInfo::OperandsMapper::createVRegs(unsigned OpIdx) { assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access"); - iterator_range::iterator> NewVRegsForOpIdx = + iterator_range::iterator> NewVRegsForOpIdx = getVRegsMem(OpIdx); const ValueMapping &ValMapping = getInstrMapping().getOperandMapping(OpIdx); const PartialMapping *PartMap = ValMapping.begin(); - for (unsigned &NewVReg : NewVRegsForOpIdx) { + for (Register &NewVReg : NewVRegsForOpIdx) { assert(PartMap != ValMapping.end() && "Out-of-bound access"); assert(NewVReg == 0 && "Register has already been created"); // The new registers are always bound to scalar with the right size. @@ -712,7 +712,7 @@ void RegisterBankInfo::OperandsMapper::createVRegs(unsigned OpIdx) { void RegisterBankInfo::OperandsMapper::setVRegs(unsigned OpIdx, unsigned PartialMapIdx, - unsigned NewVReg) { + Register NewVReg) { assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access"); assert(getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns > PartialMapIdx && @@ -724,7 +724,7 @@ void RegisterBankInfo::OperandsMapper::setVRegs(unsigned OpIdx, NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg; } -iterator_range::const_iterator> +iterator_range::const_iterator> RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx, bool ForDebug) const { (void)ForDebug; @@ -736,12 +736,12 @@ RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx, unsigned PartMapSize = getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns; - SmallVectorImpl::const_iterator End = + SmallVectorImpl::const_iterator End = getNewVRegsEnd(StartIdx, PartMapSize); - iterator_range::const_iterator> Res = + iterator_range::const_iterator> Res = make_range(&NewVRegs[StartIdx], End); #ifndef NDEBUG - for (unsigned VReg : Res) + for (Register VReg : Res) assert((VReg || ForDebug) && "Some registers are uninitialized"); #endif return Res; @@ -790,7 +790,7 @@ void RegisterBankInfo::OperandsMapper::print(raw_ostream &OS, IsFirst = false; OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", ["; bool IsFirstNewVReg = true; - for (unsigned VReg : getVRegs(Idx)) { + for (Register VReg : getVRegs(Idx)) { if (!IsFirstNewVReg) OS << ", "; IsFirstNewVReg = false;