From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Tue, 7 Feb 2017 14:22:25 +0000 (+0000)
Subject: [X86][SSE] Ensure that vector shift-by-immediate inputs are correctly bitcast to... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=cab8418968e3630a890e6519070b2237f8fb02cd;p=llvm

[X86][SSE] Ensure that vector shift-by-immediate inputs are correctly bitcast to the result type

vXi8/vXi64 vector shifts are often shifted as vYi16/vYi32 types but we weren't always remembering to bitcast the input.

Tested with a new assert as we don't currently manipulate these shifts enough for test cases to catch them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294308 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 83b340a1b5c..b3431386252 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -18479,6 +18479,11 @@ static SDValue getTargetVShiftByConstNode(unsigned Opc, const SDLoc &dl, MVT VT,
                                           SelectionDAG &DAG) {
   MVT ElementType = VT.getVectorElementType();
 
+  // Bitcast the source vector to the output type, this is mainly necessary for
+  // vXi8/vXi64 shifts.
+  if (VT != SrcOp.getSimpleValueType())
+    SrcOp = DAG.getBitcast(VT, SrcOp);
+
   // Fold this packed shift into its first operand if ShiftAmt is 0.
   if (ShiftAmt == 0)
     return SrcOp;
@@ -18495,9 +18500,8 @@ static SDValue getTargetVShiftByConstNode(unsigned Opc, const SDLoc &dl, MVT VT,
          && "Unknown target vector shift-by-constant node");
 
   // Fold this packed vector shift into a build vector if SrcOp is a
-  // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
-  if (VT == SrcOp.getSimpleValueType() &&
-      ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
+  // vector of Constants or UNDEFs.
+  if (ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
     SmallVector<SDValue, 8> Elts;
     unsigned NumElts = SrcOp->getNumOperands();
     ConstantSDNode *ND;
@@ -30523,8 +30527,10 @@ static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG,
          "Unexpected shift opcode");
   bool LogicalShift = X86ISD::VSHLI == Opcode || X86ISD::VSRLI == Opcode;
   EVT VT = N->getValueType(0);
+  SDValue N0 = N->getOperand(0);
   unsigned NumBitsPerElt = VT.getScalarSizeInBits();
-  assert((NumBitsPerElt % 8) == 0);
+  assert(VT == N0.getValueType() && (NumBitsPerElt % 8) == 0 &&
+         "Unexpected value type");
 
   // Out of range logical bit shifts are guaranteed to be zero.
   // Out of range arithmetic bit shifts splat the sign bit.
@@ -30536,8 +30542,6 @@ static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG,
       ShiftVal = NumBitsPerElt - 1;
   }
 
-  SDValue N0 = N->getOperand(0);
-
   // Shift N0 by zero -> N0.
   if (!ShiftVal)
     return N0;