From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 13 May 2019 15:31:27 +0000 (+0000)
Subject: [X86] Add SimplifyDemandedBits support for PEXTRB/PEXTRW (PR39709)
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c9601a3bcacad591804b1a78220a732175eba790;p=llvm

[X86] Add SimplifyDemandedBits support for PEXTRB/PEXTRW (PR39709)

Test case will be included in a followup - its being used but its tricky to show a case that isn't caught at a later stage anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360588 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 10632434c3d..58815524b0a 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -35112,8 +35112,13 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
   // X86ISD::PEXTRW/X86ISD::PEXTRB in:
   // XFormVExtractWithShuffleIntoLoad, combineHorizontalPredicateResult and
   // combineBasicSADPattern.
-  if (IsPextr)
+  if (IsPextr) {
+    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+    if (TLI.SimplifyDemandedBits(
+            SDValue(N, 0), APInt::getAllOnesValue(VT.getSizeInBits()), DCI))
+      return SDValue(N, 0);
     return SDValue();
+  }
 
   if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
     return NewOp;