From: Lewis Revill <lewis.revill@embecosm.com>
Date: Fri, 16 Aug 2019 10:23:56 +0000 (+0000)
Subject: [RISCV] Add inline asm constraint A for RISC-V
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c94c0391d99e127e908f2d4a9c8cf8fca0b4c044;p=clang

[RISCV] Add inline asm constraint A for RISC-V

This allows the constraint A to be used in inline asm for RISC-V, which
allows an address held in a register to be used.

This patch adds the minimal amount of code required to get operands with
the right constraints to compile.

Differential Revision: https://reviews.llvm.org/D54295



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@369093 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Basic/Targets/RISCV.cpp b/lib/Basic/Targets/RISCV.cpp
index a634ba69f3..d1166d90df 100644
--- a/lib/Basic/Targets/RISCV.cpp
+++ b/lib/Basic/Targets/RISCV.cpp
@@ -75,6 +75,10 @@ bool RISCVTargetInfo::validateAsmConstraint(
     // A floating-point register.
     Info.setAllowsRegister();
     return true;
+  case 'A':
+    // An address that is held in a general-purpose register.
+    Info.setAllowsMemory();
+    return true;
   }
 }
 
diff --git a/test/CodeGen/riscv-inline-asm.c b/test/CodeGen/riscv-inline-asm.c
index f79527337b..2c92d15ca9 100644
--- a/test/CodeGen/riscv-inline-asm.c
+++ b/test/CodeGen/riscv-inline-asm.c
@@ -38,3 +38,9 @@ void test_f() {
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}