From: Douglas Yung <douglas.yung@sony.com>
Date: Thu, 14 Mar 2019 01:24:35 +0000 (+0000)
Subject: Fixup tests to check for any MCInst number instead of a specific one.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c8c4a422420860f7d11d080f0bf5969d2bb4ebbb;p=llvm

Fixup tests to check for any MCInst number instead of a specific one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356115 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/Mips/llvm-ir/fptosi.ll b/test/CodeGen/Mips/llvm-ir/fptosi.ll
index 537e2d9b40c..03a0de74664 100644
--- a/test/CodeGen/Mips/llvm-ir/fptosi.ll
+++ b/test/CodeGen/Mips/llvm-ir/fptosi.ll
@@ -38,188 +38,188 @@
 define i32 @test1(float %t) {
 ; M32-LABEL: test1:
 ; M32:       # %bb.0: # %entry
-; M32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
+; M32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
 ; M32-NEXT:    # <MCOperand Reg:147>
 ; M32-NEXT:    # <MCOperand Reg:159>>
-; M32-NEXT:    jr $ra # <MCInst #1629 JR
+; M32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; M32-NEXT:    # <MCOperand Reg:19>>
-; M32-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M32-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M32-NEXT:    # <MCOperand Reg:321>
 ; M32-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M32R2-FP64-LABEL: test1:
 ; M32R2-FP64:       # %bb.0: # %entry
-; M32R2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
+; M32R2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:147>
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:159>>
-; M32R2-FP64-NEXT:    jr $ra # <MCInst #1629 JR
+; M32R2-FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:19>>
-; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:321>
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M32R2-SF-LABEL: test1:
 ; M32R2-SF:       # %bb.0: # %entry
-; M32R2-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #624 ADDiu
+; M32R2-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; M32R2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; M32R2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; M32R2-SF-NEXT:    # <MCInst #2520 SW
+; M32R2-SF-NEXT:    # <MCInst #{{[0-9]+}} SW
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    .cfi_offset 31, -4
-; M32R2-SF-NEXT:    jal __fixsfsi # <MCInst #1607 JAL
+; M32R2-SF-NEXT:    jal __fixsfsi # <MCInst #{{[0-9]+}} JAL
 ; M32R2-SF-NEXT:    # <MCOperand Expr:(__fixsfsi)>>
-; M32R2-SF-NEXT:    nop # <MCInst #2371 SLL
+; M32R2-SF-NEXT:    nop # <MCInst #{{[0-9]+}} SLL
 ; M32R2-SF-NEXT:    # <MCOperand Reg:21>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:21>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:0>>
 ; M32R2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; M32R2-SF-NEXT:    # <MCInst #1723 LW
+; M32R2-SF-NEXT:    # <MCInst #{{[0-9]+}} LW
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
-; M32R2-SF-NEXT:    jr $ra # <MCInst #1629 JR
+; M32R2-SF-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>>
-; M32R2-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #624 ADDiu
+; M32R2-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:24>>
 ;
 ; M32R3R5-LABEL: test1:
 ; M32R3R5:       # %bb.0: # %entry
-; M32R3R5-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
+; M32R3R5-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
 ; M32R3R5-NEXT:    # <MCOperand Reg:147>
 ; M32R3R5-NEXT:    # <MCOperand Reg:159>>
-; M32R3R5-NEXT:    jr $ra # <MCInst #1629 JR
+; M32R3R5-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; M32R3R5-NEXT:    # <MCOperand Reg:19>>
-; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M32R3R5-NEXT:    # <MCOperand Reg:321>
 ; M32R3R5-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M32R6-LABEL: test1:
 ; M32R6:       # %bb.0: # %entry
-; M32R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
+; M32R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
 ; M32R6-NEXT:    # <MCOperand Reg:147>
 ; M32R6-NEXT:    # <MCOperand Reg:159>>
-; M32R6-NEXT:    jr $ra # <MCInst #1608 JALR
+; M32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
 ; M32R6-NEXT:    # <MCOperand Reg:21>
 ; M32R6-NEXT:    # <MCOperand Reg:19>>
-; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M32R6-NEXT:    # <MCOperand Reg:321>
 ; M32R6-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M64-LABEL: test1:
 ; M64:       # %bb.0: # %entry
-; M64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
+; M64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
 ; M64-NEXT:    # <MCOperand Reg:147>
 ; M64-NEXT:    # <MCOperand Reg:159>>
-; M64-NEXT:    jr $ra # <MCInst #1629 JR
+; M64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; M64-NEXT:    # <MCOperand Reg:301>>
-; M64-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M64-NEXT:    # <MCOperand Reg:321>
 ; M64-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M64R6-LABEL: test1:
 ; M64R6:       # %bb.0: # %entry
-; M64R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
+; M64R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
 ; M64R6-NEXT:    # <MCOperand Reg:147>
 ; M64R6-NEXT:    # <MCOperand Reg:159>>
-; M64R6-NEXT:    jr $ra # <MCInst #1610 JALR64
+; M64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
 ; M64R6-NEXT:    # <MCOperand Reg:355>
 ; M64R6-NEXT:    # <MCOperand Reg:301>>
-; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M64R6-NEXT:    # <MCOperand Reg:321>
 ; M64R6-NEXT:    # <MCOperand Reg:147>>
 ;
 ; MMR2-FP32-LABEL: test1:
 ; MMR2-FP32:       # %bb.0: # %entry
-; MMR2-FP32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2639 TRUNC_W_S_MM
+; MMR2-FP32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:147>
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:159>>
-; MMR2-FP32-NEXT:    jr $ra # <MCInst #1640 JR_MM
+; MMR2-FP32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:19>>
-; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
+; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:321>
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:147>>
 ;
 ; MMR2-FP64-LABEL: test1:
 ; MMR2-FP64:       # %bb.0: # %entry
-; MMR2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2639 TRUNC_W_S_MM
+; MMR2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:147>
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:159>>
-; MMR2-FP64-NEXT:    jr $ra # <MCInst #1640 JR_MM
+; MMR2-FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:19>>
-; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
+; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:321>
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:147>>
 ;
 ; MMR2-SF-LABEL: test1:
 ; MMR2-SF:       # %bb.0: # %entry
-; MMR2-SF-NEXT:    addiusp -24 # <MCInst #561 ADDIUSP_MM
+; MMR2-SF-NEXT:    addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR2-SF-NEXT:    # <MCInst #2548 SWSP_MM
+; MMR2-SF-NEXT:    # <MCInst #{{[0-9]+}} SWSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    .cfi_offset 31, -4
-; MMR2-SF-NEXT:    jal __fixsfsi # <MCInst #1622 JAL_MM
+; MMR2-SF-NEXT:    jal __fixsfsi # <MCInst #{{[0-9]+}} JAL_MM
 ; MMR2-SF-NEXT:    # <MCOperand Expr:(__fixsfsi)>>
-; MMR2-SF-NEXT:    nop # <MCInst #2371 SLL
+; MMR2-SF-NEXT:    nop # <MCInst #{{[0-9]+}} SLL
 ; MMR2-SF-NEXT:    # <MCOperand Reg:21>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:21>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:0>>
 ; MMR2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR2-SF-NEXT:    # <MCInst #1753 LWSP_MM
+; MMR2-SF-NEXT:    # <MCInst #{{[0-9]+}} LWSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
-; MMR2-SF-NEXT:    addiusp 24 # <MCInst #561 ADDIUSP_MM
+; MMR2-SF-NEXT:    addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Imm:24>>
-; MMR2-SF-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
+; MMR2-SF-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>>
 ;
 ; MMR6-LABEL: test1:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2640 TRUNC_W_S_MMR6
+; MMR6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MMR6
 ; MMR6-NEXT:    # <MCOperand Reg:147>
 ; MMR6-NEXT:    # <MCOperand Reg:159>>
-; MMR6-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
+; MMR6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
 ; MMR6-NEXT:    # <MCOperand Reg:321>
 ; MMR6-NEXT:    # <MCOperand Reg:147>>
-; MMR6-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
 ; MMR6-NEXT:    # <MCOperand Reg:19>>
 ;
 ; MMR6-SF-LABEL: test1:
 ; MMR6-SF:       # %bb.0: # %entry
-; MMR6-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #624 ADDiu
+; MMR6-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR6-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR6-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR6-SF-NEXT:    # <MCInst #2520 SW
+; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} SW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    .cfi_offset 31, -4
-; MMR6-SF-NEXT:    jalr __fixsfsi # <MCInst #1611 JALRC16_MMR6
+; MMR6-SF-NEXT:    jalr __fixsfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
 ; MMR6-SF-NEXT:    # <MCOperand Expr:(__fixsfsi)>>
 ; MMR6-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR6-SF-NEXT:    # <MCInst #1723 LW
+; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} LW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
-; MMR6-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #624 ADDiu
+; MMR6-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:24>>
-; MMR6-SF-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
+; MMR6-SF-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>>
 entry:
   %conv = fptosi float %t to i32
@@ -229,188 +229,188 @@ entry:
 define i32 @test2(double %t) {
 ; M32-LABEL: test2:
 ; M32:       # %bb.0: # %entry
-; M32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D32
+; M32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
 ; M32-NEXT:    # <MCOperand Reg:147>
 ; M32-NEXT:    # <MCOperand Reg:133>>
-; M32-NEXT:    jr $ra # <MCInst #1629 JR
+; M32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; M32-NEXT:    # <MCOperand Reg:19>>
-; M32-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M32-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M32-NEXT:    # <MCOperand Reg:321>
 ; M32-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M32R2-FP64-LABEL: test2:
 ; M32R2-FP64:       # %bb.0: # %entry
-; M32R2-FP64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
+; M32R2-FP64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:147>
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:373>>
-; M32R2-FP64-NEXT:    jr $ra # <MCInst #1629 JR
+; M32R2-FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:19>>
-; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:321>
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M32R2-SF-LABEL: test2:
 ; M32R2-SF:       # %bb.0: # %entry
-; M32R2-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #624 ADDiu
+; M32R2-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; M32R2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; M32R2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; M32R2-SF-NEXT:    # <MCInst #2520 SW
+; M32R2-SF-NEXT:    # <MCInst #{{[0-9]+}} SW
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    .cfi_offset 31, -4
-; M32R2-SF-NEXT:    jal __fixdfsi # <MCInst #1607 JAL
+; M32R2-SF-NEXT:    jal __fixdfsi # <MCInst #{{[0-9]+}} JAL
 ; M32R2-SF-NEXT:    # <MCOperand Expr:(__fixdfsi)>>
-; M32R2-SF-NEXT:    nop # <MCInst #2371 SLL
+; M32R2-SF-NEXT:    nop # <MCInst #{{[0-9]+}} SLL
 ; M32R2-SF-NEXT:    # <MCOperand Reg:21>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:21>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:0>>
 ; M32R2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; M32R2-SF-NEXT:    # <MCInst #1723 LW
+; M32R2-SF-NEXT:    # <MCInst #{{[0-9]+}} LW
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
-; M32R2-SF-NEXT:    jr $ra # <MCInst #1629 JR
+; M32R2-SF-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>>
-; M32R2-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #624 ADDiu
+; M32R2-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:24>>
 ;
 ; M32R3R5-LABEL: test2:
 ; M32R3R5:       # %bb.0: # %entry
-; M32R3R5-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D32
+; M32R3R5-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
 ; M32R3R5-NEXT:    # <MCOperand Reg:147>
 ; M32R3R5-NEXT:    # <MCOperand Reg:133>>
-; M32R3R5-NEXT:    jr $ra # <MCInst #1629 JR
+; M32R3R5-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; M32R3R5-NEXT:    # <MCOperand Reg:19>>
-; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M32R3R5-NEXT:    # <MCOperand Reg:321>
 ; M32R3R5-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M32R6-LABEL: test2:
 ; M32R6:       # %bb.0: # %entry
-; M32R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
+; M32R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
 ; M32R6-NEXT:    # <MCOperand Reg:147>
 ; M32R6-NEXT:    # <MCOperand Reg:373>>
-; M32R6-NEXT:    jr $ra # <MCInst #1608 JALR
+; M32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
 ; M32R6-NEXT:    # <MCOperand Reg:21>
 ; M32R6-NEXT:    # <MCOperand Reg:19>>
-; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M32R6-NEXT:    # <MCOperand Reg:321>
 ; M32R6-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M64-LABEL: test2:
 ; M64:       # %bb.0: # %entry
-; M64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
+; M64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
 ; M64-NEXT:    # <MCOperand Reg:147>
 ; M64-NEXT:    # <MCOperand Reg:373>>
-; M64-NEXT:    jr $ra # <MCInst #1629 JR
+; M64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; M64-NEXT:    # <MCOperand Reg:301>>
-; M64-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M64-NEXT:    # <MCOperand Reg:321>
 ; M64-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M64R6-LABEL: test2:
 ; M64R6:       # %bb.0: # %entry
-; M64R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
+; M64R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
 ; M64R6-NEXT:    # <MCOperand Reg:147>
 ; M64R6-NEXT:    # <MCOperand Reg:373>>
-; M64R6-NEXT:    jr $ra # <MCInst #1610 JALR64
+; M64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
 ; M64R6-NEXT:    # <MCOperand Reg:355>
 ; M64R6-NEXT:    # <MCOperand Reg:301>>
-; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
+; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
 ; M64R6-NEXT:    # <MCOperand Reg:321>
 ; M64R6-NEXT:    # <MCOperand Reg:147>>
 ;
 ; MMR2-FP32-LABEL: test2:
 ; MMR2-FP32:       # %bb.0: # %entry
-; MMR2-FP32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2637 TRUNC_W_MM
+; MMR2-FP32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:147>
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:133>>
-; MMR2-FP32-NEXT:    jr $ra # <MCInst #1640 JR_MM
+; MMR2-FP32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:19>>
-; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
+; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:321>
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:147>>
 ;
 ; MMR2-FP64-LABEL: test2:
 ; MMR2-FP64:       # %bb.0: # %entry
-; MMR2-FP64-NEXT:    cvt.w.d $f0, $f12 # <MCInst #1097 CVT_W_D64_MM
+; MMR2-FP64-NEXT:    cvt.w.d $f0, $f12 # <MCInst #{{[0-9]+}} CVT_W_D64_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:147>
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:373>>
-; MMR2-FP64-NEXT:    jr $ra # <MCInst #1640 JR_MM
+; MMR2-FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:19>>
-; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
+; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:321>
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:147>>
 ;
 ; MMR2-SF-LABEL: test2:
 ; MMR2-SF:       # %bb.0: # %entry
-; MMR2-SF-NEXT:    addiusp -24 # <MCInst #561 ADDIUSP_MM
+; MMR2-SF-NEXT:    addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR2-SF-NEXT:    # <MCInst #2548 SWSP_MM
+; MMR2-SF-NEXT:    # <MCInst #{{[0-9]+}} SWSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    .cfi_offset 31, -4
-; MMR2-SF-NEXT:    jal __fixdfsi # <MCInst #1622 JAL_MM
+; MMR2-SF-NEXT:    jal __fixdfsi # <MCInst #{{[0-9]+}} JAL_MM
 ; MMR2-SF-NEXT:    # <MCOperand Expr:(__fixdfsi)>>
-; MMR2-SF-NEXT:    nop # <MCInst #2371 SLL
+; MMR2-SF-NEXT:    nop # <MCInst #{{[0-9]+}} SLL
 ; MMR2-SF-NEXT:    # <MCOperand Reg:21>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:21>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:0>>
 ; MMR2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR2-SF-NEXT:    # <MCInst #1753 LWSP_MM
+; MMR2-SF-NEXT:    # <MCInst #{{[0-9]+}} LWSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
-; MMR2-SF-NEXT:    addiusp 24 # <MCInst #561 ADDIUSP_MM
+; MMR2-SF-NEXT:    addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Imm:24>>
-; MMR2-SF-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
+; MMR2-SF-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>>
 ;
 ; MMR6-LABEL: test2:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2636 TRUNC_W_D_MMR6
+; MMR6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D_MMR6
 ; MMR6-NEXT:    # <MCOperand Reg:147>
 ; MMR6-NEXT:    # <MCOperand Reg:373>>
-; MMR6-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
+; MMR6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
 ; MMR6-NEXT:    # <MCOperand Reg:321>
 ; MMR6-NEXT:    # <MCOperand Reg:147>>
-; MMR6-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
+; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
 ; MMR6-NEXT:    # <MCOperand Reg:19>>
 ;
 ; MMR6-SF-LABEL: test2:
 ; MMR6-SF:       # %bb.0: # %entry
-; MMR6-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #624 ADDiu
+; MMR6-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR6-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR6-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR6-SF-NEXT:    # <MCInst #2520 SW
+; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} SW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    .cfi_offset 31, -4
-; MMR6-SF-NEXT:    jalr __fixdfsi # <MCInst #1611 JALRC16_MMR6
+; MMR6-SF-NEXT:    jalr __fixdfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
 ; MMR6-SF-NEXT:    # <MCOperand Expr:(__fixdfsi)>>
 ; MMR6-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR6-SF-NEXT:    # <MCInst #1723 LW
+; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} LW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
-; MMR6-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #624 ADDiu
+; MMR6-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:24>>
-; MMR6-SF-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
+; MMR6-SF-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>>
 entry:
   %conv = fptosi double %t to i32
diff --git a/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll b/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
index b63fbb940d1..3f86bd24f34 100644
--- a/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
+++ b/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
@@ -7,51 +7,51 @@
 define i64 @test(i32 signext %a, i32 signext %b) {
 ; MMR2-LABEL: test:
 ; MMR2:       # %bb.0: # %entry
-; MMR2-NEXT:    li16 $2, 0 # <MCInst #1701 LI16_MM
+; MMR2-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
 ; MMR2-NEXT:    # <MCOperand Reg:321>
 ; MMR2-NEXT:    # <MCOperand Imm:0>>
-; MMR2-NEXT:    li16 $3, 1 # <MCInst #1701 LI16_MM
+; MMR2-NEXT:    li16 $3, 1 # <MCInst #{{[0-9]+}} LI16_MM
 ; MMR2-NEXT:    # <MCOperand Reg:322>
 ; MMR2-NEXT:    # <MCOperand Imm:1>>
-; MMR2-NEXT:    mtlo $3 # <MCInst #2009 MTLO_MM
+; MMR2-NEXT:    mtlo $3 # <MCInst #{{[0-9]+}} MTLO_MM
 ; MMR2-NEXT:    # <MCOperand Reg:322>>
-; MMR2-NEXT:    mthi $2 # <MCInst #2002 MTHI_MM
+; MMR2-NEXT:    mthi $2 # <MCInst #{{[0-9]+}} MTHI_MM
 ; MMR2-NEXT:    # <MCOperand Reg:321>>
-; MMR2-NEXT:    madd $4, $5 # <MCInst #1775 MADD
+; MMR2-NEXT:    madd $4, $5 # <MCInst #{{[0-9]+}} MADD
 ; MMR2-NEXT:    # <MCOperand Reg:22>
 ; MMR2-NEXT:    # <MCOperand Reg:23>>
-; MMR2-NEXT:    mflo16 $2 # <MCInst #1861 MFLO16_MM
+; MMR2-NEXT:    mflo16 $2 # <MCInst #{{[0-9]+}} MFLO16_MM
 ; MMR2-NEXT:    # <MCOperand Reg:321>>
-; MMR2-NEXT:    mfhi16 $3 # <MCInst #1855 MFHI16_MM
+; MMR2-NEXT:    mfhi16 $3 # <MCInst #{{[0-9]+}} MFHI16_MM
 ; MMR2-NEXT:    # <MCOperand Reg:322>>
-; MMR2-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
+; MMR2-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
 ; MMR2-NEXT:    # <MCOperand Reg:19>>
 ;
 ; MMR2-DSP-LABEL: test:
 ; MMR2-DSP:       # %bb.0: # %entry
-; MMR2-DSP-NEXT:    li16 $2, 0 # <MCInst #1701 LI16_MM
+; MMR2-DSP-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:321>
 ; MMR2-DSP-NEXT:    # <MCOperand Imm:0>>
-; MMR2-DSP-NEXT:    li16 $3, 1 # <MCInst #1701 LI16_MM
+; MMR2-DSP-NEXT:    li16 $3, 1 # <MCInst #{{[0-9]+}} LI16_MM
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:322>
 ; MMR2-DSP-NEXT:    # <MCOperand Imm:1>>
-; MMR2-DSP-NEXT:    mtlo $3, $ac0 # <MCInst #2007 MTLO_DSP
+; MMR2-DSP-NEXT:    mtlo $3, $ac0 # <MCInst #{{[0-9]+}} MTLO_DSP
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:291>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:322>>
-; MMR2-DSP-NEXT:    mthi $2, $ac0 # <MCInst #2000 MTHI_DSP
+; MMR2-DSP-NEXT:    mthi $2, $ac0 # <MCInst #{{[0-9]+}} MTHI_DSP
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:253>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:321>>
-; MMR2-DSP-NEXT:    madd $ac0, $4, $5 # <MCInst #1793 MADD_DSP
+; MMR2-DSP-NEXT:    madd $ac0, $4, $5 # <MCInst #{{[0-9]+}} MADD_DSP
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:26>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:22>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:23>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:26>>
-; MMR2-DSP-NEXT:    mflo $2, $ac0 # <MCInst #1863 MFLO_DSP
+; MMR2-DSP-NEXT:    mflo $2, $ac0 # <MCInst #{{[0-9]+}} MFLO_DSP
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:321>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:26>>
-; MMR2-DSP-NEXT:    jr $ra # <MCInst #1640 JR_MM
+; MMR2-DSP-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:19>>
-; MMR2-DSP-NEXT:    mfhi $3, $ac0 # <MCInst #1857 MFHI_DSP
+; MMR2-DSP-NEXT:    mfhi $3, $ac0 # <MCInst #{{[0-9]+}} MFHI_DSP
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:322>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:26>>
 entry: