From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Sun, 19 Mar 2017 16:13:00 +0000 (+0000)
Subject: [GlobalISel] Don't select trivially dead instructions.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c86e4bce8ea96bde202e4195074445b540508afb;p=llvm

[GlobalISel] Don't select trivially dead instructions.

Folding instructions when selecting can cause them to become dead.
Don't select these dead instructions (if they don't have other side
effects, and don't define physical registers).

Preserve existing tests by adding COPYs.

In some tests, the G_CONSTANT vregs never get constrained to a class:
the only use of the vreg was folded into another instruction, so the
G_CONSTANT, now dead, never gets selected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298224 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/lib/CodeGen/GlobalISel/InstructionSelect.cpp
index 0ca4134a577..c59b200298e 100644
--- a/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+++ b/lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -48,6 +48,29 @@ void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
+/// Check whether an instruction \p MI is dead: it only defines dead virtual
+/// registers, and doesn't have other side effects.
+static bool isTriviallyDead(const MachineInstr &MI,
+                            const MachineRegisterInfo &MRI) {
+  // If we can move an instruction, we can remove it.  Otherwise, it has
+  // a side-effect of some sort.
+  bool SawStore = false;
+  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
+    return false;
+
+  // Instructions without side-effects are dead iff they only define dead vregs.
+  for (auto &MO : MI.operands()) {
+    if (!MO.isReg() || !MO.isDef())
+      continue;
+
+    unsigned Reg = MO.getReg();
+    // Keep Debug uses live: we don't want to have an effect on debug info.
+    if (TargetRegisterInfo::isPhysicalRegister(Reg) || !MRI.use_empty(Reg))
+      return false;
+  }
+  return true;
+}
+
 bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
   const MachineRegisterInfo &MRI = MF.getRegInfo();
 
@@ -119,6 +142,14 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
 
       DEBUG(dbgs() << "Selecting: \n  " << MI);
 
+      // We could have folded this instruction away already, making it dead.
+      // If so, erase it.
+      if (isTriviallyDead(MI, MRI)) {
+        DEBUG(dbgs() << "Is dead; erasing.\n");
+        MI.eraseFromParent();
+        continue;
+      }
+
       if (!ISel->select(MI)) {
         // FIXME: It would be nice to dump all inserted instructions.  It's
         // not obvious how, esp. considering select() can insert after MI.
diff --git a/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/test/CodeGen/AArch64/GlobalISel/select-binop.mir
index 92a754ffa6f..a15b56fe2d6 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-binop.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-binop.mir
@@ -83,6 +83,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_ADD %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -112,6 +113,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_ADD %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -122,7 +124,7 @@ regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32sp }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr }
 # CHECK-NEXT:  - { id: 2, class: gpr32sp }
 registers:
   - { id: 0, class: gpr }
@@ -139,6 +141,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = G_CONSTANT i32 1
     %2(s32) = G_ADD %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -149,7 +152,7 @@ regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64sp }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr }
 # CHECK-NEXT:  - { id: 2, class: gpr64sp }
 registers:
   - { id: 0, class: gpr }
@@ -166,6 +169,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = G_CONSTANT i32 1
     %2(s64) = G_ADD %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -176,7 +180,7 @@ regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32sp }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr }
 # CHECK-NEXT:  - { id: 2, class: gpr32sp }
 registers:
   - { id: 0, class: gpr }
@@ -198,6 +202,7 @@ body:             |
 
   bb.1:
     %2(s32) = G_ADD %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -227,6 +232,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_SUB %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -256,6 +262,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_SUB %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -285,6 +292,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_OR %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -314,6 +322,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_OR %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -345,6 +354,7 @@ body:             |
       %0(<2 x s32>) = COPY %d0
       %1(<2 x s32>) = COPY %d1
       %2(<2 x s32>) = G_OR %0, %1
+      %d0 = COPY %2(<2 x s32>)
 ...
 
 ---
@@ -374,6 +384,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_AND %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -403,6 +414,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_AND %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -432,6 +444,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_SHL %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -461,6 +474,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_SHL %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -490,6 +504,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_LSHR %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -519,6 +534,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_LSHR %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -548,6 +564,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_ASHR %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -577,6 +594,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_ASHR %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -607,6 +625,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_MUL %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -636,6 +655,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_MUL %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -664,6 +684,8 @@ body:             |
     %1:gpr(s64) = COPY %x1
     %2:gpr(s64) = G_SMULH %0, %1
     %3:gpr(s64) = G_UMULH %0, %1
+    %x0 = COPY %2(s64)
+    %x0 = COPY %3(s64)
 ...
 
 ---
@@ -693,6 +715,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_SDIV %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -722,6 +745,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_SDIV %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -751,6 +775,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_UDIV %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -780,6 +805,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_UDIV %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -809,6 +835,7 @@ body:             |
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
     %2(s32) = G_FADD %0, %1
+    %s0 = COPY %2(s32)
 ...
 
 ---
@@ -837,6 +864,7 @@ body:             |
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
     %2(s64) = G_FADD %0, %1
+    %d0 = COPY %2(s64)
 ...
 
 ---
@@ -865,6 +893,7 @@ body:             |
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
     %2(s32) = G_FSUB %0, %1
+    %s0 = COPY %2(s32)
 ...
 
 ---
@@ -893,6 +922,7 @@ body:             |
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
     %2(s64) = G_FSUB %0, %1
+    %d0 = COPY %2(s64)
 ...
 
 ---
@@ -921,6 +951,7 @@ body:             |
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
     %2(s32) = G_FMUL %0, %1
+    %s0 = COPY %2(s32)
 ...
 
 ---
@@ -949,6 +980,7 @@ body:             |
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
     %2(s64) = G_FMUL %0, %1
+    %d0 = COPY %2(s64)
 ...
 
 ---
@@ -977,6 +1009,7 @@ body:             |
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
     %2(s32) = G_FDIV %0, %1
+    %s0 = COPY %2(s32)
 ...
 
 ---
@@ -1005,4 +1038,5 @@ body:             |
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
     %2(s64) = G_FDIV %0, %1
+    %d0 = COPY %2(s64)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir b/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
index 2770d780130..5ca63dbc214 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
@@ -34,6 +34,7 @@ body:             |
 
     %0(s32) = COPY %w0
     %1(s32) = G_BITCAST %0
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -58,6 +59,7 @@ body:             |
 
     %0(s32) = COPY %s0
     %1(s32) = G_BITCAST %0
+    %s0 = COPY %1(s32)
 ...
 
 ---
@@ -82,6 +84,7 @@ body:             |
 
     %0(s32) = COPY %w0
     %1(s32) = G_BITCAST %0
+    %s0 = COPY %1(s32)
 ...
 
 ---
@@ -106,6 +109,7 @@ body:             |
 
     %0(s32) = COPY %s0
     %1(s32) = G_BITCAST %0
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -130,6 +134,7 @@ body:             |
 
     %0(s64) = COPY %x0
     %1(s64) = G_BITCAST %0
+    %x0 = COPY %1(s64)
 ...
 
 ---
@@ -154,6 +159,7 @@ body:             |
 
     %0(s64) = COPY %d0
     %1(s64) = G_BITCAST %0
+    %d0 = COPY %1(s64)
 ...
 
 ---
@@ -177,6 +183,7 @@ body:             |
 
     %0(s64) = COPY %x0
     %1(s64) = G_BITCAST %0
+    %d0 = COPY %1(s64)
 ...
 
 ---
@@ -201,4 +208,5 @@ body:             |
 
     %0(s64) = COPY %d0
     %1(s64) = G_BITCAST %0
+    %x0 = COPY %1(s64)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/test/CodeGen/AArch64/GlobalISel/select-constant.mir
index b9953246666..1a5bac9fb7d 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-constant.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-constant.mir
@@ -23,6 +23,7 @@ registers:
 body:             |
   bb.0:
     %0(s32) = G_CONSTANT i32 42
+    %w0 = COPY %0(s32)
 ...
 
 ---
@@ -38,6 +39,7 @@ registers:
 body:             |
   bb.0:
     %0(s64) = G_CONSTANT i64 1234567890123
+    %x0 = COPY %0(s64)
 ...
 
 ---
@@ -54,6 +56,7 @@ registers:
 body:             |
   bb.0:
     %0(s32) = G_FCONSTANT float 3.5
+    %s0 = COPY %0(s32)
 ...
 
 ---
@@ -70,4 +73,5 @@ registers:
 body:             |
   bb.0:
     %0(s64) = G_FCONSTANT double 1.0
+    %d0 = COPY %0(s64)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
index b703fb5c495..fbb11a1c7a4 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
@@ -49,6 +49,7 @@ body:             |
 
     %0(s64) = COPY %d0
     %1(s32) = G_FPTRUNC %0
+    %s0 = COPY %1(s32)
 ...
 
 ---
@@ -73,6 +74,7 @@ body:             |
 
     %0(s32) = COPY %s0
     %1(s64) = G_FPEXT %0
+    %d0 = COPY %1(s64)
 ...
 
 ---
@@ -97,6 +99,7 @@ body:             |
 
     %0(s32) = COPY %w0
     %1(s32) = G_SITOFP %0
+    %s0 = COPY %1(s32)
 ...
 
 ---
@@ -121,6 +124,7 @@ body:             |
 
     %0(s64) = COPY %x0
     %1(s32) = G_SITOFP %0
+    %s0 = COPY %1(s32)
 ...
 
 ---
@@ -145,6 +149,7 @@ body:             |
 
     %0(s32) = COPY %w0
     %1(s64) = G_SITOFP %0
+    %d0 = COPY %1(s64)
 ...
 
 ---
@@ -169,6 +174,7 @@ body:             |
 
     %0(s64) = COPY %x0
     %1(s64) = G_SITOFP %0
+    %d0 = COPY %1(s64)
 ...
 
 ---
@@ -193,6 +199,7 @@ body:             |
 
     %0(s32) = COPY %w0
     %1(s32) = G_UITOFP %0
+    %s0 = COPY %1(s32)
 ...
 
 ---
@@ -217,6 +224,7 @@ body:             |
 
     %0(s64) = COPY %x0
     %1(s32) = G_UITOFP %0
+    %s0 = COPY %1(s32)
 ...
 
 ---
@@ -241,6 +249,7 @@ body:             |
 
     %0(s32) = COPY %w0
     %1(s64) = G_UITOFP %0
+    %d0 = COPY %1(s64)
 ...
 
 ---
@@ -265,6 +274,7 @@ body:             |
 
     %0(s64) = COPY %x0
     %1(s64) = G_UITOFP %0
+    %d0 = COPY %1(s64)
 ...
 
 ---
@@ -289,6 +299,7 @@ body:             |
 
     %0(s32) = COPY %s0
     %1(s32) = G_FPTOSI %0
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -313,6 +324,7 @@ body:             |
 
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOSI %0
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -337,6 +349,7 @@ body:             |
 
     %0(s32) = COPY %s0
     %1(s64) = G_FPTOSI %0
+    %x0 = COPY %1(s64)
 ...
 
 ---
@@ -361,6 +374,7 @@ body:             |
 
     %0(s64) = COPY %d0
     %1(s64) = G_FPTOSI %0
+    %x0 = COPY %1(s64)
 ...
 
 ---
@@ -385,6 +399,7 @@ body:             |
 
     %0(s32) = COPY %s0
     %1(s32) = G_FPTOUI %0
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -409,6 +424,7 @@ body:             |
 
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOUI %0
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -433,6 +449,7 @@ body:             |
 
     %0(s32) = COPY %s0
     %1(s64) = G_FPTOUI %0
+    %x0 = COPY %1(s64)
 ...
 
 ---
@@ -457,4 +474,5 @@ body:             |
 
     %0(s64) = COPY %d0
     %1(s64) = G_FPTOUI %0
+    %x0 = COPY %1(s64)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
index 5680122edfb..b5da3e60bd2 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
@@ -39,6 +39,7 @@ body:             |
 
     %0(s32) = COPY %w0
     %1(s64) = G_ANYEXT %0
+    %x0 = COPY %1(s64)
 ...
 
 ---
@@ -63,6 +64,7 @@ body:             |
 
     %0(s8) = COPY %w0
     %1(s32) = G_ANYEXT %0
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -89,6 +91,7 @@ body:             |
 
     %0(s32) = COPY %w0
     %1(s64) = G_ZEXT %0
+    %x0 = COPY %1(s64)
 ...
 
 ---
@@ -113,6 +116,7 @@ body:             |
 
     %0(s8) = COPY %w0
     %1(s32) = G_ZEXT %0
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -137,6 +141,7 @@ body:             |
 
     %0(s8) = COPY %w0
     %1(s16) = G_ZEXT %0
+    %w0 = COPY %1(s16)
 ...
 
 ---
@@ -163,6 +168,7 @@ body:             |
 
     %0(s32) = COPY %w0
     %1(s64) = G_SEXT %0
+    %x0 = COPY %1(s64)
 ...
 
 ---
@@ -187,6 +193,7 @@ body:             |
 
     %0(s8) = COPY %w0
     %1(s32) = G_SEXT %0
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -211,4 +218,5 @@ body:             |
 
     %0(s8) = COPY %w0
     %1(s16) = G_SEXT %0
+    %w0 = COPY %1(s16)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir b/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
index 9fa82ddc4d5..6537408f6d9 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
@@ -31,6 +31,7 @@ body:             |
     liveins: %x0
     %0(s64) = COPY %x0
     %1(p0) = G_INTTOPTR %0
+    %x0 = COPY %1(p0)
 ...
 
 ---
@@ -53,6 +54,7 @@ body:             |
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s64) = G_PTRTOINT %0
+    %x0 = COPY %1(s64)
 ...
 
 ---
@@ -75,6 +77,7 @@ body:             |
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s32) = G_PTRTOINT %0
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -97,6 +100,7 @@ body:             |
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s16) = G_PTRTOINT %0
+    %w0 = COPY %1(s16)
 ...
 
 ---
@@ -119,6 +123,7 @@ body:             |
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s8) = G_PTRTOINT %0
+    %w0 = COPY %1(s8)
 ...
 
 ---
@@ -141,4 +146,5 @@ body:             |
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s1) = G_PTRTOINT %0
+    %w0 = COPY %1(s1)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-load.mir b/test/CodeGen/AArch64/GlobalISel/select-load.mir
index 5c91990d644..0821fc76446 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-load.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-load.mir
@@ -35,7 +35,7 @@ body:             |
 
     %0(p0) = COPY %x0
     %1(s64) = G_LOAD  %0 :: (load 8 from %ir.addr)
-
+    %x0 = COPY %1(s64)
 ...
 
 ---
@@ -60,7 +60,7 @@ body:             |
 
     %0(p0) = COPY %x0
     %1(s32) = G_LOAD  %0 :: (load 4 from %ir.addr)
-
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -85,7 +85,7 @@ body:             |
 
     %0(p0) = COPY %x0
     %1(s16) = G_LOAD  %0 :: (load 2 from %ir.addr)
-
+    %w0 = COPY %1(s16)
 ...
 
 ---
@@ -110,7 +110,7 @@ body:             |
 
     %0(p0) = COPY %x0
     %1(s8) = G_LOAD  %0 :: (load 1 from %ir.addr)
-
+    %w0 = COPY %1(s8)
 ...
 
 ---
@@ -135,7 +135,7 @@ body:             |
 
     %0(p0) = COPY %x0
     %1(s64) = G_LOAD  %0 :: (load 8 from %ir.addr)
-
+    %d0 = COPY %1(s64)
 ...
 
 ---
@@ -160,7 +160,7 @@ body:             |
 
     %0(p0) = COPY %x0
     %1(s32) = G_LOAD  %0 :: (load 4 from %ir.addr)
-
+    %s0 = COPY %1(s32)
 ...
 
 ---
@@ -185,7 +185,7 @@ body:             |
 
     %0(p0) = COPY %x0
     %1(s16) = G_LOAD  %0 :: (load 2 from %ir.addr)
-
+    %h0 = COPY %1(s16)
 ...
 
 ---
@@ -210,5 +210,5 @@ body:             |
 
     %0(p0) = COPY %x0
     %1(s8) = G_LOAD  %0 :: (load 1 from %ir.addr)
-
+    %b0 = COPY %1(s8)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-trunc.mir b/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
index e0e04407e9c..fc3546e777f 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
@@ -29,6 +29,7 @@ body:             |
 
     %0(s64) = COPY %x0
     %1(s32) = G_TRUNC %0
+    %w0 = COPY %1(s32)
 ...
 
 ---
@@ -52,6 +53,7 @@ body:             |
 
     %0(s64) = COPY %x0
     %1(s8) = G_TRUNC %0
+    %w0 = COPY %1(s8)
 ...
 
 ---
@@ -75,4 +77,5 @@ body:             |
 
     %0(s32) = COPY %w0
     %1(s1) = G_TRUNC %0
+    %w0 = COPY %1(s1)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-xor.mir b/test/CodeGen/AArch64/GlobalISel/select-xor.mir
index c8e67c8737e..05c0b021332 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-xor.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-xor.mir
@@ -39,6 +39,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_XOR %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -68,6 +69,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_XOR %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -80,7 +82,7 @@ regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
   - { id: 0, class: gpr }
@@ -97,6 +99,7 @@ body:             |
     %0(s32) = COPY %w0
     %1(s32) = G_CONSTANT i64 -1
     %2(s32) = G_XOR %0, %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -108,7 +111,7 @@ regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
   - { id: 0, class: gpr }
@@ -125,6 +128,7 @@ body:             |
     %0(s64) = COPY %x0
     %1(s64) = G_CONSTANT i64 -1
     %2(s64) = G_XOR %0, %1
+    %x0 = COPY %2(s64)
 ...
 
 ---
@@ -136,7 +140,7 @@ regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
   - { id: 0, class: gpr }
@@ -157,4 +161,5 @@ body:             |
   bb.1:
     %0(s32) = COPY %w0
     %2(s32) = G_XOR %0, %1
+    %w0 = COPY %2(s32)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select.mir b/test/CodeGen/AArch64/GlobalISel/select.mir
index 645975b4d27..8bffa085fdc 100644
--- a/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -47,6 +47,7 @@ stack:
 body:             |
   bb.0:
     %0(p0) = G_FRAME_INDEX %stack.0.ptr0
+    %x0 = COPY %0(p0)
 ...
 
 ---
@@ -68,6 +69,7 @@ body:             |
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 42
     %2(p0) = G_GEP %0, %1(s64)
+    %x0 = COPY %2(p0)
 ...
 
 ---
@@ -83,6 +85,7 @@ body:             |
       liveins: %x0
     %0:gpr(p0) = COPY %x0
     %1:gpr(p0) = G_PTR_MASK %0, 3
+    %x0 = COPY %1(p0)
 ...
 
 ---
@@ -101,6 +104,7 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @var_local
+    %x0 = COPY %0(p0)
 ...
 
 ---
@@ -118,6 +122,7 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @var_got
+    %x0 = COPY %0(p0)
 ...
 
 ---
@@ -157,12 +162,15 @@ body:             |
 
     %0(s32) = COPY %w0
     %1(s1) = G_ICMP intpred(eq), %0, %0
+    %w0 = COPY %1(s1)
 
     %2(s64) = COPY %x0
     %3(s1) = G_ICMP intpred(uge), %2, %2
+    %w0 = COPY %3(s1)
 
     %4(p0) = COPY %x0
     %5(s1) = G_ICMP intpred(ne), %4, %4
+    %w0 = COPY %5(s1)
 ...
 
 ---
@@ -199,9 +207,11 @@ body:             |
 
     %0(s32) = COPY %s0
     %1(s1) = G_FCMP floatpred(one), %0, %0
+    %w0 = COPY %1(s1)
 
     %2(s64) = COPY %d0
     %3(s1) = G_FCMP floatpred(uge), %2, %2
+    %w0 = COPY %3(s1)
 
 ...
 
@@ -287,12 +297,15 @@ body:             |
     %1(s32) = COPY %w1
     %2(s32) = COPY %w2
     %3(s32) = G_SELECT %0, %1, %2
+    %w0 = COPY %3(s32)
 
     %4(s64) = COPY %x0
     %5(s64) = COPY %x1
     %6(s64) = G_SELECT %0, %4, %5
+    %x0 = COPY %6(s64)
 
     %7(p0) = COPY %x0
     %8(p0) = COPY %x1
     %9(p0) = G_SELECT %0, %7, %8
+    %x0 = COPY %9(p0)
 ...
diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
index c78ed11b73e..e10ffa00c43 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
@@ -22,6 +22,7 @@ body: |
 
     %0:vgpr(p1) = COPY %vgpr0_vgpr1
     %1:vgpr(s32) = G_LOAD %0 :: (load 4 from %ir.global0)
+    %vgpr0 = COPY %1
 
 ...
 ---
diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
index e23852b74a4..78bf9d8e352 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
@@ -25,25 +25,18 @@ regBankSelected: true
 # VI:   S_LOAD_DWORD_IMM [[PTR]], 1020, 0
 
 # Immediate overflow for SI
-# FIXME: The immediate gets selected twice, once into the
-# S_LOAD_DWORD instruction and once just as a normal constat.
-# SI: S_MOV_B32 1024
 # SI: [[K1024:%[0-9]+]] = S_MOV_B32 1024
 # SI: S_LOAD_DWORD_SGPR [[PTR]], [[K1024]], 0
 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 256, 0
 # VI: S_LOAD_DWORD_IMM [[PTR]], 1024, 0
 
 # Max immediate offset for VI
-# SI: S_MOV_B32 1048572
 # SI: [[K1048572:%[0-9]+]] = S_MOV_B32 1048572
 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262143
 # VI: S_LOAD_DWORD_IMM [[PTR]], 1048572
 
 #
 # Immediate overflow for VI
-# FIXME: The immediate gets selected twice, once into the
-# S_LOAD_DWORD instruction and once just as a normal constat.
-# SIVI: S_MOV_B32 1048576
 # SIVI: [[K1048576:%[0-9]+]] = S_MOV_B32 1048576
 # SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K1048576]], 0
 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262144, 0
@@ -76,9 +69,6 @@ regBankSelected: true
 # GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
 
 # Max 32-bit byte offset
-# FIXME: The immediate gets selected twice, once into the
-# S_LOAD_DWORD instruction and once just as a normal constat.
-# SIVI: S_MOV_B32 4294967292
 # SIVI: [[K4294967292:%[0-9]+]] = S_MOV_B32 4294967292
 # SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K4294967292]], 0
 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741823, 0
@@ -106,38 +96,47 @@ body: |
     %1:sgpr(s64) = G_CONSTANT i64 4
     %2:sgpr(p2) = G_GEP %0, %1
     %3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0)
+    %sgpr0 = COPY %3
 
     %4:sgpr(s64) = G_CONSTANT i64 1020
     %5:sgpr(p2) = G_GEP %0, %4
     %6:sgpr(s32) = G_LOAD %5 :: (load 4 from %ir.const0)
+    %sgpr0 = COPY %6
 
     %7:sgpr(s64) = G_CONSTANT i64 1024
     %8:sgpr(p2) = G_GEP %0, %7
     %9:sgpr(s32) = G_LOAD %8 :: (load 4 from %ir.const0)
+    %sgpr0 = COPY %9
 
     %10:sgpr(s64) = G_CONSTANT i64 1048572
     %11:sgpr(p2) = G_GEP %0, %10
     %12:sgpr(s32) = G_LOAD %11 :: (load 4 from %ir.const0)
+    %sgpr0 = COPY %12
 
     %13:sgpr(s64) = G_CONSTANT i64 1048576
     %14:sgpr(p2) = G_GEP %0, %13
     %15:sgpr(s32) = G_LOAD %14 :: (load 4 from %ir.const0)
+    %sgpr0 = COPY %15
 
     %16:sgpr(s64) = G_CONSTANT i64 17179869180
     %17:sgpr(p2) = G_GEP %0, %16
     %18:sgpr(s32) = G_LOAD %17 :: (load 4 from %ir.const0)
+    %sgpr0 = COPY %18
 
     %19:sgpr(s64) = G_CONSTANT i64 17179869184
     %20:sgpr(p2) = G_GEP %0, %19
     %21:sgpr(s32) = G_LOAD %20 :: (load 4 from %ir.const0)
+    %sgpr0 = COPY %21
 
     %22:sgpr(s64) = G_CONSTANT i64 4294967292
     %23:sgpr(p2) = G_GEP %0, %22
     %24:sgpr(s32) = G_LOAD %23 :: (load 4 from %ir.const0)
+    %sgpr0 = COPY %24
 
     %25:sgpr(s64) = G_CONSTANT i64 4294967296
     %26:sgpr(p2) = G_GEP %0, %25
     %27:sgpr(s32) = G_LOAD %26 :: (load 4 from %ir.const0)
+    %sgpr0 = COPY %27
 
 ...
 ---
diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index 28224b40880..66d9033a6d7 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -326,13 +326,19 @@ body:             |
     ; CHECK: [[FI32VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI32]], 0, 14, _, _
 
     %1(s32) = G_LOAD %0(p0) :: (load 4)
-    ; CHECK: {{%[0-9]+}} = LDRi12 [[FI32VREG]], 0, 14, _
+    ; CHECK: [[LD32VREG:%[0-9]+]] = LDRi12 [[FI32VREG]], 0, 14, _
+
+    %r0 = COPY %1
+    ; CHECK: %r0 = COPY [[LD32VREG]]
 
     %2(p0) = G_FRAME_INDEX %fixed-stack.0
     ; CHECK: [[FI1VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI1]], 0, 14, _, _
 
     %3(s1) = G_LOAD %2(p0) :: (load 1)
-    ; CHECK: {{%[0-9]+}} = LDRBi12 [[FI1VREG]], 0, 14, _
+    ; CHECK: [[LD1VREG:%[0-9]+]] = LDRBi12 [[FI1VREG]], 0, 14, _
+
+    %r0 = COPY %3
+    ; CHECK: %r0 = COPY [[LD1VREG]]
 
     BX_RET 14, _
     ; CHECK: BX_RET 14, _
diff --git a/test/CodeGen/X86/GlobalISel/x86_64-instructionselect.mir b/test/CodeGen/X86/GlobalISel/x86_64-instructionselect.mir
index 7aa1a4e6966..a4f6f2d6da9 100644
--- a/test/CodeGen/X86/GlobalISel/x86_64-instructionselect.mir
+++ b/test/CodeGen/X86/GlobalISel/x86_64-instructionselect.mir
@@ -87,6 +87,7 @@ body:             |
     %0(s64) = COPY %rdi
     %1(s64) = COPY %rsi
     %2(s64) = G_ADD %0, %1
+    %rax = COPY %2(s64)
 
 ...
 
@@ -112,6 +113,7 @@ body:             |
     %0(s32) = COPY %edi
     %1(s32) = COPY %esi
     %2(s32) = G_ADD %0, %1
+    %rax = COPY %2(s32)
 
 ...
 
@@ -137,6 +139,7 @@ body:             |
     %0(s64) = COPY %rdi
     %1(s64) = COPY %rsi
     %2(s64) = G_SUB %0, %1
+    %rax = COPY %2(s64)
 
 ...
 
@@ -162,6 +165,7 @@ body:             |
     %0(s32) = COPY %edi
     %1(s32) = COPY %esi
     %2(s32) = G_SUB %0, %1
+    %rax = COPY %2(s32)
 
 ...