From: Petar Avramovic <Petar.Avramovic@rt-rk.com>
Date: Thu, 5 Sep 2019 11:16:37 +0000 (+0000)
Subject: [MIPS GlobalISel] Select llvm.trap intrinsic
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c80ed278312095e47201cf352ef525975ff9ee4c;p=llvm

[MIPS GlobalISel] Select llvm.trap intrinsic

Select G_INTRINSIC_W_SIDE_EFFECTS for Intrinsic::trap for MIPS32
via legalizeIntrinsic.

Differential Revision: https://reviews.llvm.org/D67180


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371055 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsLegalizerInfo.cpp b/lib/Target/Mips/MipsLegalizerInfo.cpp
index d4de79c10a2..80a24a3ab42 100644
--- a/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -219,8 +219,16 @@ bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
   return true;
 }
 
-bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
+bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
+                                          MachineRegisterInfo &MRI,
                                           MachineIRBuilder &MIRBuilder) const {
+  const MipsSubtarget &ST =
+      static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget());
+  const MipsInstrInfo &TII = *ST.getInstrInfo();
+  const MipsRegisterInfo &TRI = *ST.getRegisterInfo();
+  const RegisterBankInfo &RBI = *ST.getRegBankInfo();
+  MIRBuilder.setInstr(MI);
+
   switch (MI.getIntrinsicID()) {
   case Intrinsic::memcpy:
   case Intrinsic::memset:
@@ -230,6 +238,11 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo
       return false;
     MI.eraseFromParent();
     return true;
+  case Intrinsic::trap: {
+    MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP);
+    MI.eraseFromParent();
+    return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
+  }
   default:
     break;
   }
diff --git a/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir b/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir
new file mode 100644
index 00000000000..101a12490b7
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir
@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  declare void @llvm.trap()
+  define void @f() { ret void }
+
+...
+---
+name:            f
+alignment:       2
+body:             |
+  bb.1 (%ir-block.0):
+    ; MIPS32-LABEL: name: f
+    ; MIPS32: TRAP
+    ; MIPS32: RetRA
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
+    RetRA
+
+...
+
+
diff --git a/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll b/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll
new file mode 100644
index 00000000000..cf71f5f5677
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+  declare void @llvm.trap()
+
+  define void @f() {
+; MIPS32-LABEL: f:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    break
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+    call void @llvm.trap()
+    ret void
+  }