From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Fri, 3 May 2019 15:08:36 +0000 (+0000)
Subject: AMDGPU: Remove redundant patterns for shifts
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c79eef95e31698e51fa35d3d6c5534f78f694c03;p=llvm

AMDGPU: Remove redundant patterns for shifts

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359895 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/VOP2Instructions.td b/lib/Target/AMDGPU/VOP2Instructions.td
index 33b4cb774a5..3d7c75a3a04 100644
--- a/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/lib/Target/AMDGPU/VOP2Instructions.td
@@ -519,11 +519,9 @@ class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
       )
   >;
 
-let AddedComplexity = 1 in {
-  def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
-  def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
-  def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
-}
+def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
+def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
+def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
 
 let SubtargetPredicate = HasAddNoCarryInsts in {
   def : DivergentBinOp<add, V_ADD_U32_e32>;
@@ -534,12 +532,9 @@ let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] i
 def : DivergentBinOp<add, V_ADD_I32_e32>;
 def : DivergentBinOp<sub, V_SUB_I32_e32>;
 
-def : DivergentBinOp<srl, V_LSHRREV_B32_e32>;
-def : DivergentBinOp<sra, V_ASHRREV_I32_e32>;
-def : DivergentBinOp<shl, V_LSHLREV_B32_e32>;
-}
 def : DivergentBinOp<adde, V_ADDC_U32_e32>;
 def : DivergentBinOp<sube, V_SUBB_U32_e32>;
+}
 
 class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> :
   GCNPat<