From: Craig Topper <craig.topper@gmail.com>
Date: Mon, 13 Mar 2017 00:36:49 +0000 (+0000)
Subject: [AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory opera... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c68171ad8f91cd6097152768d9ea0ceabac078ac;p=llvm

[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead.

This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297596 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/evex-to-vex-compress.mir b/test/CodeGen/X86/evex-to-vex-compress.mir
index 138cd540cce..8b28ea1d03f 100755
--- a/test/CodeGen/X86/evex-to-vex-compress.mir
+++ b/test/CodeGen/X86/evex-to-vex-compress.mir
@@ -2172,7 +2172,7 @@ body: |
   %rdi = VCVTSS2SI64Zrr                        %xmm0                                                   
   ; CHECK: %edi = VCVTSS2SIrr                  %xmm0
   %edi = VCVTSS2SIZrr                          %xmm0                                                   
-  ; CHECK: %rdi = VCVTTSD2SI64rm               %rdi, %xmm0, 1, _, 0
+  ; CHECK: %rdi = Int_VCVTTSD2SI64rm           %rdi, %xmm0, 1, _, 0
   %rdi = VCVTTSD2SI64Zrm                       %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %rdi = Int_VCVTTSD2SI64rm           %rdi, %xmm0, 1, _, 0
   %rdi = VCVTTSD2SI64Zrm_Int                   %rdi, %xmm0, 1, _, 0                                    
@@ -2180,7 +2180,7 @@ body: |
   %rdi = VCVTTSD2SI64Zrr                       %xmm0                                                   
   ; CHECK: %rdi = Int_VCVTTSD2SI64rr           %xmm0
   %rdi = VCVTTSD2SI64Zrr_Int                   %xmm0                                                   
-  ; CHECK: %edi = VCVTTSD2SIrm                 %rdi, %xmm0, 1, _, 0
+  ; CHECK: %edi = Int_VCVTTSD2SIrm             %rdi, %xmm0, 1, _, 0
   %edi = VCVTTSD2SIZrm                         %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %edi = Int_VCVTTSD2SIrm             %rdi, %xmm0, 1, _, 0
   %edi = VCVTTSD2SIZrm_Int                     %rdi, %xmm0, 1, _, 0                                    
@@ -2188,7 +2188,7 @@ body: |
   %edi = VCVTTSD2SIZrr                         %xmm0                                                   
   ; CHECK: %edi = Int_VCVTTSD2SIrr             %xmm0
   %edi = VCVTTSD2SIZrr_Int                     %xmm0                                                   
-  ; CHECK: %rdi = VCVTTSS2SI64rm               %rdi, %xmm0, 1, _, 0
+  ; CHECK: %rdi = Int_VCVTTSS2SI64rm           %rdi, %xmm0, 1, _, 0
   %rdi = VCVTTSS2SI64Zrm                       %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %rdi = Int_VCVTTSS2SI64rm           %rdi, %xmm0, 1, _, 0
   %rdi = VCVTTSS2SI64Zrm_Int                   %rdi, %xmm0, 1, _, 0                                    
@@ -2196,7 +2196,7 @@ body: |
   %rdi = VCVTTSS2SI64Zrr                       %xmm0                                                   
   ; CHECK: %rdi = Int_VCVTTSS2SI64rr           %xmm0
   %rdi = VCVTTSS2SI64Zrr_Int                   %xmm0                                                   
-  ; CHECK: %edi = VCVTTSS2SIrm                 %rdi, %xmm0, 1, _, 0
+  ; CHECK: %edi = Int_VCVTTSS2SIrm             %rdi, %xmm0, 1, _, 0
   %edi = VCVTTSS2SIZrm                         %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %edi = Int_VCVTTSS2SIrm             %rdi, %xmm0, 1, _, 0
   %edi = VCVTTSS2SIZrm_Int                     %rdi, %xmm0, 1, _, 0                                    
diff --git a/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp b/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
index 24f84aec6ca..142a969d340 100644
--- a/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
+++ b/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
@@ -72,7 +72,8 @@ private:
       "VPSRAQ",
       "VDBPSADBW",
       "VRNDSCALE",
-      "VSCALEFPS"
+      "VSCALEFPS",
+      "VSCALEFSS",
   };
 
   bool inExceptionList(const CodeGenInstruction *Inst) {
@@ -242,7 +243,7 @@ public:
         if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
           return false;
       } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
-          return false;
+        continue;
       } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
         if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type"))
           return false;