From: Krzysztof Parzyszek Date: Fri, 13 Oct 2017 21:57:11 +0000 (+0000) Subject: Revert r315763: "[Hexagon] Rangify some loops, NFC" X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c5d47386152071ccc150523bebbe13b56e8b8be3;p=llvm Revert r315763: "[Hexagon] Rangify some loops, NFC" Broke some builds (using libstdc++). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315769 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Hexagon/BitTracker.cpp b/lib/Target/Hexagon/BitTracker.cpp index f12b192e882..0b0d48a011e 100644 --- a/lib/Target/Hexagon/BitTracker.cpp +++ b/lib/Target/Hexagon/BitTracker.cpp @@ -181,8 +181,8 @@ namespace llvm { } // end namespace llvm void BitTracker::print_cells(raw_ostream &OS) const { - for (const std::pair P : Map) - dbgs() << PrintReg(P.first, &ME.TRI) << " -> " << P.second << "\n"; + for (CellMapType::iterator I = Map.begin(), E = Map.end(); I != E; ++I) + dbgs() << PrintReg(I->first, &ME.TRI) << " -> " << I->second << "\n"; } BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F) @@ -830,16 +830,18 @@ void BT::visitNonBranch(const MachineInstr &MI) { << " cell: " << ME.getCell(RU, Map) << "\n"; } dbgs() << "Outputs:\n"; - for (const std::pair &P : ResMap) { - RegisterRef RD(P.first); - dbgs() << " " << PrintReg(P.first, &ME.TRI) << " cell: " + for (CellMapType::iterator I = ResMap.begin(), E = ResMap.end(); + I != E; ++I) { + RegisterRef RD(I->first); + dbgs() << " " << PrintReg(I->first, &ME.TRI) << " cell: " << ME.getCell(RD, ResMap) << "\n"; } } // Iterate over all definitions of the instruction, and update the // cells accordingly. - for (const MachineOperand &MO : MI.operands()) { + for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) { + const MachineOperand &MO = MI.getOperand(i); // Visit register defs only. if (!MO.isReg() || !MO.isDef()) continue; @@ -924,11 +926,14 @@ void BT::visitBranchesFrom(const MachineInstr &BI) { ++It; } while (FallsThrough && It != End); + using succ_iterator = MachineBasicBlock::const_succ_iterator; + if (!DefaultToAll) { // Need to add all CFG successors that lead to EH landing pads. // There won't be explicit branches to these blocks, but they must // be processed. - for (const MachineBasicBlock *SB : B.successors()) { + for (succ_iterator I = B.succ_begin(), E = B.succ_end(); I != E; ++I) { + const MachineBasicBlock *SB = *I; if (SB->isEHPad()) Targets.insert(SB); } @@ -939,27 +944,33 @@ void BT::visitBranchesFrom(const MachineInstr &BI) { Targets.insert(&*Next); } } else { - for (const MachineBasicBlock *SB : B.successors()) - Targets.insert(SB); + for (succ_iterator I = B.succ_begin(), E = B.succ_end(); I != E; ++I) + Targets.insert(*I); } - for (const MachineBasicBlock *TB : Targets) - FlowQ.push(CFGEdge(ThisN, TB->getNumber())); + for (unsigned i = 0, n = Targets.size(); i < n; ++i) { + int TargetN = Targets[i]->getNumber(); + FlowQ.push(CFGEdge(ThisN, TargetN)); + } } void BT::visitUsesOf(unsigned Reg) { if (Trace) dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n"; - for (const MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) { - if (!InstrExec.count(&UseI)) + using use_iterator = MachineRegisterInfo::use_nodbg_iterator; + + use_iterator End = MRI.use_nodbg_end(); + for (use_iterator I = MRI.use_nodbg_begin(Reg); I != End; ++I) { + MachineInstr *UseI = I->getParent(); + if (!InstrExec.count(UseI)) continue; - if (UseI.isPHI()) - visitPHI(UseI); - else if (!UseI.isBranch()) - visitNonBranch(UseI); + if (UseI->isPHI()) + visitPHI(*UseI); + else if (!UseI->isBranch()) + visitNonBranch(*UseI); else - visitBranchesFrom(UseI); + visitBranchesFrom(*UseI); } } @@ -982,8 +993,8 @@ void BT::subst(RegisterRef OldRR, RegisterRef NewRR) { (void)NME; assert((OME-OMB == NME-NMB) && "Substituting registers of different lengths"); - for (std::pair P : Map) { - RegisterCell &RC = P.second; + for (CellMapType::iterator I = Map.begin(), E = Map.end(); I != E; ++I) { + RegisterCell &RC = I->second; for (uint16_t i = 0, w = RC.width(); i < w; ++i) { BitValue &V = RC[i]; if (V.Type != BitValue::Ref || V.RefI.Reg != OldRR.Reg) @@ -1034,9 +1045,10 @@ void BT::run() { const MachineBasicBlock *Entry = MachineFlowGraphTraits::getEntryNode(&MF); unsigned MaxBN = 0; - for (const MachineBasicBlock &B : MF) { - assert(B.getNumber() >= 0 && "Disconnected block"); - unsigned BN = B.getNumber(); + for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); + I != E; ++I) { + assert(I->getNumber() >= 0 && "Disconnected block"); + unsigned BN = I->getNumber(); if (BN > MaxBN) MaxBN = BN; } diff --git a/lib/Target/Hexagon/HexagonBitTracker.cpp b/lib/Target/Hexagon/HexagonBitTracker.cpp index e62e006e40c..08e08fe5087 100644 --- a/lib/Target/Hexagon/HexagonBitTracker.cpp +++ b/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -60,8 +60,12 @@ HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri, // der the initial sequence of formal parameters that are known to be // passed via registers. unsigned InVirtReg, InPhysReg = 0; + const Function &F = *MF.getFunction(); - for (const Argument &Arg : MF.getFunction()->args()) { + using arg_iterator = Function::const_arg_iterator; + + for (arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { + const Argument &Arg = *I; Type *ATy = Arg.getType(); unsigned Width = 0; if (ATy->isIntegerTy()) @@ -186,7 +190,8 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI, unsigned NumDefs = 0; // Sanity verification: there should not be any defs with subregisters. - for (const MachineOperand &MO : MI.operands()) { + for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) { + const MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || !MO.isDef()) continue; NumDefs++; @@ -235,7 +240,8 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI, // checking what kind of operand a given instruction has individually // for each instruction, do it here. Global symbols as operands gene- // rally do not provide any useful information. - for (const MachineOperand &MO : MI.operands()) { + for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) { + const MachineOperand &MO = MI.getOperand(i); if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() || MO.isCPI()) return false;