From: Coby Tayree <coby.tayree@intel.com>
Date: Thu, 28 Sep 2017 11:04:08 +0000 (+0000)
Subject: [x86][AsmParser] Allow some more MS size directives
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c4a1886529aeb7ec19427ef4f7ba03db67230c48;p=llvm

[x86][AsmParser] Allow some more MS size directives
MS allows the following size directives: float/double and long as synonymous to dword/qword and dword, respectively.
Differential Revision: https://reviews.llvm.org/D37190


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314410 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 880cfcca33d..bd176bac4c4 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1689,7 +1689,10 @@ bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
     .Cases("BYTE", "byte", 8)
     .Cases("WORD", "word", 16)
     .Cases("DWORD", "dword", 32)
+    .Cases("FLOAT", "float", 32)
+    .Cases("LONG", "long", 32)
     .Cases("FWORD", "fword", 48)
+    .Cases("DOUBLE", "double", 64)
     .Cases("QWORD", "qword", 64)
     .Cases("MMWORD","mmword", 64)
     .Cases("XWORD", "xword", 80)
diff --git a/test/MC/X86/intel-syntax.s b/test/MC/X86/intel-syntax.s
index 352544e4c77..21bec91d83a 100644
--- a/test/MC/X86/intel-syntax.s
+++ b/test/MC/X86/intel-syntax.s
@@ -693,11 +693,13 @@ fadd   dword ptr "?half@?0??bar@@YAXXZ@4NA"@IMGREL
 // CHECK: fadds   "?half@?0??bar@@YAXXZ@4NA"@IMGREL
 
 inc qword ptr [rax]
+inc long ptr [rax]
 inc dword ptr [rax]
 inc word ptr [rax]
 inc byte ptr [rax]
 // CHECK: incq (%rax)
 // CHECK: incl (%rax)
+// CHECK: incl (%rax)
 // CHECK: incw (%rax)
 // CHECK: incb (%rax)
 
@@ -807,6 +809,11 @@ fbstp tbyte ptr [eax]
 // CHECK: fbld (%eax)
 // CHECK: fbstp (%eax)
 
+fld float ptr [rax]
+fld double ptr [rax]
+// CHECK: flds (%rax)
+// CHECK: fldl (%rax)
+
 fcomip st, st(2)
 fucomip st, st(2)
 // CHECK: fcompi  %st(2)