From: Amara Emerson <aemerson@apple.com>
Date: Tue, 13 Aug 2019 23:51:20 +0000 (+0000)
Subject: [AArch64][GlobalISel] RBS: Treat s128s like vectors when unmerging.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c403e44218b79997b2b76832aa2d5c74c5a3b17c;p=llvm

[AArch64][GlobalISel] RBS: Treat s128s like vectors when unmerging.

The destinations should be FPRs (for now).

Differential Revision: https://reviews.llvm.org/D66184

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368775 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index 63cdf326ac3..8ec73aa3c04 100644
--- a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -768,7 +768,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
     // UNMERGE into scalars from a vector should always use FPR.
     // Likewise if any of the uses are FP instructions.
-    if (SrcTy.isVector() ||
+    if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||
         any_of(MRI.use_instructions(MI.getOperand(0).getReg()),
                [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) {
       // Set the register bank of every operand to FPR.
diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
index 3123de27c1e..d1032548090 100644
--- a/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
+++ b/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
@@ -24,3 +24,27 @@ body:             |
     RET_ReallyLR implicit $x0
 
 ...
+---
+name:            unmerge_s128
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+frameInfo:
+  maxCallFrameSize: 0
+body:             |
+  bb.0:
+    liveins: $q0
+
+    ; s128 should be treated as an FPR/vector because it can't live on GPR bank.
+    ; CHECK-LABEL: name: unmerge_s128
+    ; CHECK: liveins: $q0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s128) = COPY $q0
+    ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+    ; CHECK: $x0 = COPY [[UV]](s64)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %0:_(s128) = COPY $q0
+    %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(s128)
+    $x0 = COPY %1(s64)
+    RET_ReallyLR implicit $x0
+
+...