From: David Green <david.green@arm.com>
Date: Tue, 5 Mar 2019 11:18:55 +0000 (+0000)
Subject: [SCEV] Add some extra tests for IndVarSimplifys loop exit values. NFC.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c3ee69937015ddc534169bb9040f89856279bff7;p=llvm

[SCEV] Add some extra tests for IndVarSimplifys loop exit values. NFC.

Add some tests for various loops of the form:
  while(S >= 32) {
    S -= 32;
    something();
  };
  return S;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355389 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/Transforms/IndVarSimplify/replace-loop-exit-folds.ll b/test/Transforms/IndVarSimplify/replace-loop-exit-folds.ll
new file mode 100644
index 00000000000..02bf7692736
--- /dev/null
+++ b/test/Transforms/IndVarSimplify/replace-loop-exit-folds.ll
@@ -0,0 +1,232 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -indvars -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+
+define i32 @remove_loop(i32 %size) {
+; CHECK-LABEL: @remove_loop(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 -1, [[SIZE:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], -32
+; CHECK-NEXT:    [[UMAX:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 -32
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[SIZE]], [[UMAX]]
+; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[TMP2]], 32
+; CHECK-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 5
+; CHECK-NEXT:    [[TMP5:%.*]] = shl i32 [[TMP4]], 5
+; CHECK-NEXT:    br label [[WHILE_COND:%.*]]
+; CHECK:       while.cond:
+; CHECK-NEXT:    [[SIZE_ADDR_0:%.*]] = phi i32 [ [[SIZE]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[WHILE_COND]] ]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[SIZE_ADDR_0]], 31
+; CHECK-NEXT:    [[SUB]] = add i32 [[SIZE_ADDR_0]], -32
+; CHECK-NEXT:    br i1 [[CMP]], label [[WHILE_COND]], label [[WHILE_END:%.*]]
+; CHECK:       while.end:
+; CHECK-NEXT:    [[TMP6:%.*]] = sub i32 [[SIZE]], [[TMP5]]
+; CHECK-NEXT:    ret i32 [[TMP6]]
+;
+entry:
+  br label %while.cond
+
+while.cond:                                       ; preds = %while.cond, %entry
+  %size.addr.0 = phi i32 [ %size, %entry ], [ %sub, %while.cond ]
+  %cmp = icmp ugt i32 %size.addr.0, 31
+  %sub = add i32 %size.addr.0, -32
+  br i1 %cmp, label %while.cond, label %while.end
+
+while.end:                                        ; preds = %while.cond
+  %size.lcssa = phi i32 [ %size.addr.0, %while.cond ]
+  ret i32 %size.lcssa
+}
+
+define i32 @used_loop(i32 %size) minsize {
+; CHECK-LABEL: @used_loop(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 -1, [[SIZE:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], -32
+; CHECK-NEXT:    [[UMAX:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 -32
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[SIZE]], [[UMAX]]
+; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[TMP2]], 32
+; CHECK-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 5
+; CHECK-NEXT:    [[TMP5:%.*]] = shl i32 [[TMP4]], 5
+; CHECK-NEXT:    br label [[WHILE_COND:%.*]]
+; CHECK:       while.cond:
+; CHECK-NEXT:    [[SIZE_ADDR_0:%.*]] = phi i32 [ [[SIZE]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[WHILE_COND]] ]
+; CHECK-NEXT:    tail call void @call()
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[SIZE_ADDR_0]], 31
+; CHECK-NEXT:    [[SUB]] = add i32 [[SIZE_ADDR_0]], -32
+; CHECK-NEXT:    br i1 [[CMP]], label [[WHILE_COND]], label [[WHILE_END:%.*]]
+; CHECK:       while.end:
+; CHECK-NEXT:    [[TMP6:%.*]] = sub i32 [[SIZE]], [[TMP5]]
+; CHECK-NEXT:    ret i32 [[TMP6]]
+;
+entry:
+  br label %while.cond
+
+while.cond:                                       ; preds = %while.cond, %entry
+  %size.addr.0 = phi i32 [ %size, %entry ], [ %sub, %while.cond ]
+  tail call void @call()
+  %cmp = icmp ugt i32 %size.addr.0, 31
+  %sub = add i32 %size.addr.0, -32
+  br i1 %cmp, label %while.cond, label %while.end
+
+while.end:                                        ; preds = %while.cond
+  %size.lcssa = phi i32 [ %size.addr.0, %while.cond ]
+  ret i32 %size.lcssa
+}
+
+
+define i32 @test_signed_while(i32 %S) {
+; CHECK-LABEL: @test_signed_while(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 -1, [[S:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], -32
+; CHECK-NEXT:    [[SMAX:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 -32
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[S]], [[SMAX]]
+; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[TMP2]], 32
+; CHECK-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 5
+; CHECK-NEXT:    [[TMP5:%.*]] = shl i32 [[TMP4]], 5
+; CHECK-NEXT:    br label [[WHILE_COND:%.*]]
+; CHECK:       while.cond:
+; CHECK-NEXT:    [[S_ADDR_0:%.*]] = phi i32 [ [[S]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[WHILE_BODY:%.*]] ]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[S_ADDR_0]], 31
+; CHECK-NEXT:    br i1 [[CMP]], label [[WHILE_BODY]], label [[WHILE_END:%.*]]
+; CHECK:       while.body:
+; CHECK-NEXT:    [[SUB]] = add nsw i32 [[S_ADDR_0]], -32
+; CHECK-NEXT:    tail call void @call()
+; CHECK-NEXT:    br label [[WHILE_COND]]
+; CHECK:       while.end:
+; CHECK-NEXT:    [[TMP6:%.*]] = sub i32 [[S]], [[TMP5]]
+; CHECK-NEXT:    ret i32 [[TMP6]]
+;
+entry:
+  br label %while.cond
+
+while.cond:                                       ; preds = %while.body, %entry
+  %S.addr.0 = phi i32 [ %S, %entry ], [ %sub, %while.body ]
+  %cmp = icmp sgt i32 %S.addr.0, 31
+  br i1 %cmp, label %while.body, label %while.end
+
+while.body:                                       ; preds = %while.cond
+  %sub = add nsw i32 %S.addr.0, -32
+  tail call void @call()
+  br label %while.cond
+
+while.end:                                        ; preds = %while.cond
+  %S.addr.0.lcssa = phi i32 [ %S.addr.0, %while.cond ]
+  ret i32 %S.addr.0.lcssa
+}
+
+define i32 @test_signed_do(i32 %S) {
+; CHECK-LABEL: @test_signed_do(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 15, [[S:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], -16
+; CHECK-NEXT:    [[SMAX:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 -16
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[S]], [[SMAX]]
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP2]], 4
+; CHECK-NEXT:    [[TMP4:%.*]] = shl i32 [[TMP3]], 4
+; CHECK-NEXT:    br label [[DO_BODY:%.*]]
+; CHECK:       do.body:
+; CHECK-NEXT:    [[S_ADDR_0:%.*]] = phi i32 [ [[S]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[DO_BODY]] ]
+; CHECK-NEXT:    [[SUB]] = add nsw i32 [[S_ADDR_0]], -16
+; CHECK-NEXT:    tail call void @call()
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[SUB]], 15
+; CHECK-NEXT:    br i1 [[CMP]], label [[DO_BODY]], label [[DO_END:%.*]]
+; CHECK:       do.end:
+; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[S]], -16
+; CHECK-NEXT:    [[TMP6:%.*]] = sub i32 [[TMP5]], [[TMP4]]
+; CHECK-NEXT:    ret i32 [[TMP6]]
+;
+entry:
+  br label %do.body
+
+do.body:                                          ; preds = %do.body, %entry
+  %S.addr.0 = phi i32 [ %S, %entry ], [ %sub, %do.body ]
+  %sub = add nsw i32 %S.addr.0, -16
+  tail call void @call()
+  %cmp = icmp sgt i32 %sub, 15
+  br i1 %cmp, label %do.body, label %do.end
+
+do.end:                                           ; preds = %do.body
+  %sub.lcssa = phi i32 [ %sub, %do.body ]
+  ret i32 %sub.lcssa
+}
+
+define i32 @test_unsigned_while(i32 %S) {
+; CHECK-LABEL: @test_unsigned_while(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 -1, [[S:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], -16
+; CHECK-NEXT:    [[UMAX:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 -16
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[S]], [[UMAX]]
+; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[TMP2]], 16
+; CHECK-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 4
+; CHECK-NEXT:    [[TMP5:%.*]] = shl i32 [[TMP4]], 4
+; CHECK-NEXT:    br label [[WHILE_COND:%.*]]
+; CHECK:       while.cond:
+; CHECK-NEXT:    [[S_ADDR_0:%.*]] = phi i32 [ [[S]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[WHILE_BODY:%.*]] ]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[S_ADDR_0]], 15
+; CHECK-NEXT:    br i1 [[CMP]], label [[WHILE_BODY]], label [[WHILE_END:%.*]]
+; CHECK:       while.body:
+; CHECK-NEXT:    [[SUB]] = add i32 [[S_ADDR_0]], -16
+; CHECK-NEXT:    tail call void @call()
+; CHECK-NEXT:    br label [[WHILE_COND]]
+; CHECK:       while.end:
+; CHECK-NEXT:    [[TMP6:%.*]] = sub i32 [[S]], [[TMP5]]
+; CHECK-NEXT:    ret i32 [[TMP6]]
+;
+entry:
+  br label %while.cond
+
+while.cond:                                       ; preds = %while.body, %entry
+  %S.addr.0 = phi i32 [ %S, %entry ], [ %sub, %while.body ]
+  %cmp = icmp ugt i32 %S.addr.0, 15
+  br i1 %cmp, label %while.body, label %while.end
+
+while.body:                                       ; preds = %while.cond
+  %sub = add i32 %S.addr.0, -16
+  tail call void @call()
+  br label %while.cond
+
+while.end:                                        ; preds = %while.cond
+  %S.addr.0.lcssa = phi i32 [ %S.addr.0, %while.cond ]
+  ret i32 %S.addr.0.lcssa
+}
+
+define i32 @test_unsigned_do(i32 %S) {
+; CHECK-LABEL: @test_unsigned_do(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 15, [[S:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], -16
+; CHECK-NEXT:    [[UMAX:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 -16
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[S]], [[UMAX]]
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP2]], 4
+; CHECK-NEXT:    [[TMP4:%.*]] = shl i32 [[TMP3]], 4
+; CHECK-NEXT:    br label [[DO_BODY:%.*]]
+; CHECK:       do.body:
+; CHECK-NEXT:    [[S_ADDR_0:%.*]] = phi i32 [ [[S]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[DO_BODY]] ]
+; CHECK-NEXT:    [[SUB]] = add i32 [[S_ADDR_0]], -16
+; CHECK-NEXT:    tail call void @call()
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[SUB]], 15
+; CHECK-NEXT:    br i1 [[CMP]], label [[DO_BODY]], label [[DO_END:%.*]]
+; CHECK:       do.end:
+; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[S]], -16
+; CHECK-NEXT:    [[TMP6:%.*]] = sub i32 [[TMP5]], [[TMP4]]
+; CHECK-NEXT:    ret i32 [[TMP6]]
+;
+entry:
+  br label %do.body
+
+do.body:                                          ; preds = %do.body, %entry
+  %S.addr.0 = phi i32 [ %S, %entry ], [ %sub, %do.body ]
+  %sub = add i32 %S.addr.0, -16
+  tail call void @call()
+  %cmp = icmp ugt i32 %sub, 15
+  br i1 %cmp, label %do.body, label %do.end
+
+do.end:                                           ; preds = %do.body
+  %sub.lcssa = phi i32 [ %sub, %do.body ]
+  ret i32 %sub.lcssa
+}
+
+
+declare void @call()