From: Craig Topper <craig.topper@intel.com>
Date: Fri, 24 May 2019 04:46:56 +0000 (+0000)
Subject: [X86] Add test case that was supposed to go with r360102.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c39c565309e58bb4ac153c66a647fce7c1e38f57;p=llvm

[X86] Add test case that was supposed to go with r360102.

Found in my working area. Guess I forgot 'git add' before committing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361599 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/asm-reg-type-mismatch-avx512.ll b/test/CodeGen/X86/asm-reg-type-mismatch-avx512.ll
new file mode 100644
index 00000000000..1c5e1ce8a6b
--- /dev/null
+++ b/test/CodeGen/X86/asm-reg-type-mismatch-avx512.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx512f | FileCheck %s
+
+define i64 @test1() nounwind {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    vmovq {{.*#+}} xmm16 = mem[0],zero
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    vmovq %xmm16, %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i64 asm sideeffect "vmovq $1, $0", "={xmm16},*m,~{dirflag},~{fpsr},~{flags}"(i64* null) nounwind
+  ret i64 %0
+}