From: David Majnemer Date: Tue, 21 Jun 2016 05:10:24 +0000 (+0000) Subject: Replace silly uses of 'signed' with 'int' X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=c1362817c9d40f61ffbdbe81a61c82bfde171e4b;p=llvm Replace silly uses of 'signed' with 'int' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273244 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/ADT/StringRef.h b/include/llvm/ADT/StringRef.h index 97ba177e546..398ca692024 100644 --- a/include/llvm/ADT/StringRef.h +++ b/include/llvm/ADT/StringRef.h @@ -10,6 +10,7 @@ #ifndef LLVM_ADT_STRINGREF_H #define LLVM_ADT_STRINGREF_H +#include "llvm/ADT/iterator_range.h" #include "llvm/Support/Compiler.h" #include #include @@ -101,6 +102,9 @@ namespace llvm { const unsigned char *bytes_end() const { return reinterpret_cast(end()); } + iterator_range bytes() const { + return make_range(bytes_begin(), bytes_end()); + } /// @} /// @name String Operations diff --git a/include/llvm/CodeGen/ResourcePriorityQueue.h b/include/llvm/CodeGen/ResourcePriorityQueue.h index 0097e0472e5..9c8f5f487d3 100644 --- a/include/llvm/CodeGen/ResourcePriorityQueue.h +++ b/include/llvm/CodeGen/ResourcePriorityQueue.h @@ -72,7 +72,7 @@ namespace llvm { /// Heuristics for estimating register pressure. unsigned ParallelLiveRanges; - signed HorizontalVerticalBalance; + int HorizontalVerticalBalance; public: ResourcePriorityQueue(SelectionDAGISel *IS); @@ -103,14 +103,14 @@ namespace llvm { /// Single cost function reflecting benefit of scheduling SU /// in the current cycle. - signed SUSchedulingCost (SUnit *SU); + int SUSchedulingCost (SUnit *SU); /// InitNumRegDefsLeft - Determine the # of regs defined by this node. /// void initNumRegDefsLeft(SUnit *SU); void updateNumRegDefsLeft(SUnit *SU); - signed regPressureDelta(SUnit *SU, bool RawPressure = false); - signed rawRegPressureDelta (SUnit *SU, unsigned RCId); + int regPressureDelta(SUnit *SU, bool RawPressure = false); + int rawRegPressureDelta (SUnit *SU, unsigned RCId); bool empty() const override { return Queue.empty(); } diff --git a/lib/Analysis/ConstantFolding.cpp b/lib/Analysis/ConstantFolding.cpp index 677c3d92d02..5bf5539f5c9 100644 --- a/lib/Analysis/ConstantFolding.cpp +++ b/lib/Analysis/ConstantFolding.cpp @@ -17,6 +17,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Analysis/ConstantFolding.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringMap.h" @@ -564,7 +565,7 @@ Constant *llvm::ConstantFoldLoadFromConstPtr(Constant *C, Type *Ty, // directly if string length is small enough. StringRef Str; if (getConstantStringInfo(CE, Str) && !Str.empty()) { - unsigned StrLen = Str.size(); + size_t StrLen = Str.size(); unsigned NumBits = Ty->getPrimitiveSizeInBits(); // Replace load with immediate integer if the result is an integer or fp // value. @@ -573,15 +574,13 @@ Constant *llvm::ConstantFoldLoadFromConstPtr(Constant *C, Type *Ty, APInt StrVal(NumBits, 0); APInt SingleChar(NumBits, 0); if (DL.isLittleEndian()) { - for (signed i = StrLen-1; i >= 0; i--) { - SingleChar = (uint64_t) Str[i] & - std::numeric_limits::max(); + for (unsigned char C : reverse(Str.bytes())) { + SingleChar = static_cast(C); StrVal = (StrVal << 8) | SingleChar; } } else { - for (unsigned i = 0; i < StrLen; i++) { - SingleChar = (uint64_t) Str[i] & - std::numeric_limits::max(); + for (unsigned char C : Str.bytes()) { + SingleChar = static_cast(C); StrVal = (StrVal << 8) | SingleChar; } // Append NULL at the end. diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8e823a37ee3..e9e68b72fa6 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4692,7 +4692,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) { TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements()); // Determine the residual right-shift amount. - signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); + int ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); // If the shift is not a no-op (in which case this should be just a sign // extend already), the truncated to type is legal, sign_extend is legal diff --git a/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp b/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp index 622e06f0da2..1e5c4a73693 100644 --- a/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp +++ b/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp @@ -37,7 +37,7 @@ static cl::opt DisableDFASched("disable-dfa-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable use of DFA during scheduling")); -static cl::opt RegPressureThreshold( +static cl::opt RegPressureThreshold( "dfa-sched-reg-pressure-threshold", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Track reg pressure and switch priority to in-depth")); @@ -323,8 +323,8 @@ void ResourcePriorityQueue::reserveResources(SUnit *SU) { } } -signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) { - signed RegBalance = 0; +int ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) { + int RegBalance = 0; if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode()) return RegBalance; @@ -357,8 +357,8 @@ signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) { /// The RawPressure flag makes this function to ignore /// existing reg file sizes, and report raw def/use /// balance. -signed ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool RawPressure) { - signed RegBalance = 0; +int ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool RawPressure) { + int RegBalance = 0; if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode()) return RegBalance; @@ -398,9 +398,9 @@ static const unsigned FactorOne = 2; /// Returns single number reflecting benefit of scheduling SU /// in the current cycle. -signed ResourcePriorityQueue::SUSchedulingCost(SUnit *SU) { +int ResourcePriorityQueue::SUSchedulingCost(SUnit *SU) { // Initial trivial priority. - signed ResCount = 1; + int ResCount = 1; // Do not waste time on a node that is already scheduled. if (SU->isScheduled) @@ -601,7 +601,7 @@ SUnit *ResourcePriorityQueue::pop() { std::vector::iterator Best = Queue.begin(); if (!DisableDFASched) { - signed BestCost = SUSchedulingCost(*Best); + int BestCost = SUSchedulingCost(*Best); for (std::vector::iterator I = std::next(Queue.begin()), E = Queue.end(); I != E; ++I) { diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 1d22da7fb4e..d98615527f0 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -9475,14 +9475,13 @@ bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) { // isEquivalentMaskless() is the code for testing if the AND can be removed // factored out of the DAG recognition as the DAG can take several forms. -static -bool isEquivalentMaskless(unsigned CC, unsigned width, - ISD::LoadExtType ExtType, signed AddConstant, - signed CompConstant) { +static bool isEquivalentMaskless(unsigned CC, unsigned width, + ISD::LoadExtType ExtType, int AddConstant, + int CompConstant) { // By being careful about our equations and only writing the in term // symbolic values and well known constants (0, 1, -1, MaxUInt) we can // make them generally applicable to all bit widths. - signed MaxUInt = (1 << width); + int MaxUInt = (1 << width); // For the purposes of these comparisons sign extending the type is // equivalent to zero extending the add and displacing it by half the integer diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index b824d118bc2..5e8459db38d 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -931,7 +931,7 @@ void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr, // ARM halfword load/stores and signed byte loads need an additional // operand. if (useAM3) { - signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; + int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; MIB.addReg(0); MIB.addImm(Imm); } else { @@ -945,7 +945,7 @@ void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr, // ARM halfword load/stores and signed byte loads need an additional // operand. if (useAM3) { - signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; + int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; MIB.addReg(0); MIB.addImm(Imm); } else { diff --git a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 985215ac385..6cf5f505fea 100644 --- a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -1797,15 +1797,13 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, MCOperand &MO = Inst.getOperand(1); int64_t Value; if (MO.getExpr()->evaluateAsAbsolute(Value)) { - unsigned long long u64 = Value; - signed int s8 = (u64 >> 32) & 0xFFFFFFFF; - if (s8 < -128 || s8 > 127) + int s8 = Hi_32(Value); + if (!isInt<8>(s8)) OutOfRange(IDLoc, s8, -128); MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create( MCConstantExpr::create(s8, Context), Context))); // upper 32 auto Expr = HexagonMCExpr::create( - MCConstantExpr::create(u64 & 0xFFFFFFFF, Context), - Context); + MCConstantExpr::create(Lo_32(Value), Context), Context); HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr())); MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index 7d37b42ef4d..cab8a0b34a1 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -416,12 +416,12 @@ public: uint32_t Offset = Fixup.getOffset(); unsigned NumBytes = getFixupKindNumBytes(Kind); assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); - char* InstAddr = Data + Offset; + char *InstAddr = Data + Offset; Value = adjustFixupValue(Kind, FixupValue); if(!Value) return; - signed sValue = (signed)Value; + int sValue = (int)Value; switch((unsigned)Kind) { default: diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp index aeb2df61e2a..a7ddd775273 100644 --- a/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -516,7 +516,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, unsigned VR = MF.getRegInfo().createVirtualRegister(RC); assert(isInt<16>(MFI->getMaxAlignment()) && "Function's alignment size requirement is not supported."); - int MaxAlign = - (signed) MFI->getMaxAlignment(); + int MaxAlign = -(int)MFI->getMaxAlignment(); BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign); BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR); diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index e78a3ba580b..d33ff95c684 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -262,7 +262,7 @@ def HI16 : SDNodeXFormgetZExtValue(); + int Val = N->getZExtValue(); return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); }]>; def MB : SDNodeXFormop_begin()+1, E = PN->op_end(); I !=E; ++I) { GetElementPtrInst *Op2 = dyn_cast(*I);