From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Wed, 15 Mar 2017 19:20:59 +0000 (+0000)
Subject: [GlobalISel][AArch64] Select ADDXri.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=bde5be06dbc1d6873d50205b0aebd48c71c8294f;p=llvm

[GlobalISel][AArch64] Select ADDXri.

We're now able to select ADDWri thanks to the new complex pattern
support.  Extend that to ADDXri.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297874 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/Target/GlobalISel/Target.td b/include/llvm/Target/GlobalISel/Target.td
index b4ca2f88fb3..fa1a424b589 100644
--- a/include/llvm/Target/GlobalISel/Target.td
+++ b/include/llvm/Target/GlobalISel/Target.td
@@ -22,6 +22,7 @@
 class LLT;
 
 def s32 : LLT;
+def s64 : LLT;
 
 // Defines a matcher for complex operands. This is analogous to ComplexPattern
 // from SelectionDAG.
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index d57e1db1d33..6da730618e0 100644
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -693,6 +693,10 @@ def gi_addsub_shifted_imm32 :
     GIComplexOperandMatcher<s32, (ops i32imm, i32imm), "selectArithImmed">,
     GIComplexPatternEquiv<addsub_shifted_imm32>;
 
+def gi_addsub_shifted_imm64 :
+    GIComplexOperandMatcher<s64, (ops i32imm, i32imm), "selectArithImmed">,
+    GIComplexPatternEquiv<addsub_shifted_imm64>;
+
 class neg_addsub_shifted_imm<ValueType Ty>
     : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
   let PrintMethod = "printAddSubImm";
diff --git a/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/test/CodeGen/AArch64/GlobalISel/select-binop.mir
index 9d7ecf488fe..c922af710dc 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-binop.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-binop.mir
@@ -7,6 +7,8 @@
   define void @add_s64_gpr() { ret void }
 
   define void @add_imm_s32_gpr() { ret void }
+  define void @add_imm_s64_gpr() { ret void }
+
   define void @add_imm_s32_gpr_bb() { ret void }
 
   define void @sub_s32_gpr() { ret void }
@@ -139,6 +141,33 @@ body:             |
     %2(s32) = G_ADD %0, %1
 ...
 
+---
+# CHECK-LABEL: name: add_imm_s64_gpr
+name:            add_imm_s64_gpr
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64sp }
+# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 2, class: gpr64sp }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %x0
+# CHECK:    %2 = ADDXri %0, 1, 0
+body:             |
+  bb.0:
+    liveins: %x0, %w1
+
+    %0(s64) = COPY %x0
+    %1(s64) = G_CONSTANT 1
+    %2(s64) = G_ADD %0, %1
+...
+
 ---
 # CHECK-LABEL: name: add_imm_s32_gpr_bb
 name:            add_imm_s32_gpr_bb