From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 6 Feb 2017 18:57:51 +0000 (+0000)
Subject: [X86][SSE] Add tests showing missed opportunities to simplify integer absolute instru... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=bc8099138a78ce2b34f64f9490a1cb51c583dd38;p=llvm

[X86][SSE] Add tests showing missed opportunities to simplify integer absolute instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294216 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/combine-abs.ll b/test/CodeGen/X86/combine-abs.ll
new file mode 100644
index 00000000000..fbf40f9e378
--- /dev/null
+++ b/test/CodeGen/X86/combine-abs.ll
@@ -0,0 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s
+
+; FIXME: Various missed opportunities to simplify integer absolute instructions.
+
+; fold (abs c1) -> c2
+define <4 x i32> @combine_v4i32_abs_constant() {
+; CHECK-LABEL: combine_v4i32_abs_constant:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpabsd {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %1 = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> <i32 0, i32 -1, i32 3, i32 -2147483648>)
+  ret <4 x i32> %1
+}
+
+define <16 x i16> @combine_v16i16_abs_constant() {
+; CHECK-LABEL: combine_v16i16_abs_constant:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpabsw {{.*}}(%rip), %ymm0
+; CHECK-NEXT:    retq
+  %1 = call <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16> <i16 0, i16 1, i16 -1, i16 3, i16 -3, i16 7, i16 -7, i16 255, i16 -255, i16 4096, i16 -4096, i16 32767, i16 -32767, i16 -32768, i16 32768, i16 65536>)
+  ret <16 x i16> %1
+}
+
+; fold (abs (abs x)) -> (abs x)
+define <8 x i16> @combine_v8i16_abs_abs(<8 x i16> %a) {
+; CHECK-LABEL: combine_v8i16_abs_abs:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpabsw %xmm0, %xmm0
+; CHECK-NEXT:    vpabsw %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %1 = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a)
+  %2 = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %1)
+  ret <8 x i16> %2
+}
+
+define <32 x i8> @combine_v32i8_abs_abs(<32 x i8> %a) {
+; CHECK-LABEL: combine_v32i8_abs_abs:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpabsb %ymm0, %ymm0
+; CHECK-NEXT:    vpabsb %ymm0, %ymm0
+; CHECK-NEXT:    retq
+  %1 = call <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8> %a)
+  %2 = call <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8> %1)
+  ret <32 x i8> %2
+}
+
+; fold (abs x) -> x iff not-negative
+define <16 x i8> @combine_v16i8_abs_constant(<16 x i8> %a) {
+; CHECK-LABEL: combine_v16i8_abs_constant:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    vpabsb %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %1 = insertelement <16 x i8> undef, i8 15, i32 0
+  %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer
+  %3 = and <16 x i8> %a, %2
+  %4 = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %3)
+  ret <16 x i8> %4
+}
+
+define <8 x i32> @combine_v8i32_abs_pos(<8 x i32> %a) {
+; CHECK-LABEL: combine_v8i32_abs_pos:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrld $1, %ymm0, %ymm0
+; CHECK-NEXT:    vpabsd %ymm0, %ymm0
+; CHECK-NEXT:    retq
+  %1 = lshr <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  %2 = call <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32> %1)
+  ret <8 x i32> %2
+}
+
+declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
+declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
+
+declare <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8>) nounwind readnone
+declare <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32>) nounwind readnone
+declare <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16>) nounwind readnone