From: Diana Picus <diana.picus@linaro.org>
Date: Thu, 20 Jul 2017 11:36:03 +0000 (+0000)
Subject: Revert "GlobalISel: select G_EXTRACT and G_INSERT instructions on AArch64."
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=bacda5f6878f7766d8c78a3d235114160071678d;p=llvm

Revert "GlobalISel: select G_EXTRACT and G_INSERT instructions on AArch64."

This reverts commit 36c6a2ea9669bc3bb695928529a85d12d1d3e3f9 because it
broke the test-suite on the GlobalISel bot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308603 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 58a261f749f..43f3daf8a03 100644
--- a/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -758,54 +758,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
     constrainSelectedInstRegOperands(I, TII, TRI, RBI);
     return true;
   }
-  case TargetOpcode::G_EXTRACT: {
-    LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
-    // Larger extracts are vectors, same-size extracts should be something else
-    // by now (either split up or simplified to a COPY).
-    if (SrcTy.getSizeInBits() > 64 || Ty.getSizeInBits() > 32)
-      return false;
-
-    I.setDesc(TII.get(AArch64::UBFMXri));
-    MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() +
-                                      Ty.getSizeInBits() - 1);
-
-    unsigned DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
-    BuildMI(MBB, std::next(I.getIterator()), I.getDebugLoc(),
-            TII.get(AArch64::COPY))
-        .addDef(I.getOperand(0).getReg())
-        .addUse(DstReg, 0, AArch64::sub_32);
-    RBI.constrainGenericRegister(I.getOperand(0).getReg(),
-                                 AArch64::GPR32RegClass, MRI);
-    I.getOperand(0).setReg(DstReg);
-
-    return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
-  }
-  case TargetOpcode::G_INSERT: {
-    LLT SrcTy = MRI.getType(I.getOperand(2).getReg());
-    // Larger inserts are vectors, same-size ones should be something else by
-    // now (split up or turned into COPYs).
-    if (Ty.getSizeInBits() > 64 || SrcTy.getSizeInBits() > 32)
-      return false;
-
-    I.setDesc(TII.get(AArch64::BFMXri));
-    unsigned LSB = I.getOperand(3).getImm();
-    unsigned Width = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
-    I.getOperand(3).setImm((64 - LSB) % 64);
-    MachineInstrBuilder(MF, I).addImm(Width - 1);
-
-    unsigned SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
-    BuildMI(MBB, I.getIterator(), I.getDebugLoc(),
-            TII.get(AArch64::SUBREG_TO_REG))
-        .addDef(SrcReg)
-        .addImm(0)
-        .addUse(I.getOperand(2).getReg())
-        .addImm(AArch64::sub_32);
-    RBI.constrainGenericRegister(I.getOperand(2).getReg(),
-                                 AArch64::GPR32RegClass, MRI);
-    I.getOperand(2).setReg(SrcReg);
-
-    return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
-  }
   case TargetOpcode::G_FRAME_INDEX: {
     // allocas and G_FRAME_INDEX are only supported in addrspace(0).
     if (Ty != LLT::pointer(0, 64)) {
@@ -813,6 +765,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
             << ", expected: " << LLT::pointer(0, 64) << '\n');
       return false;
     }
+
     I.setDesc(TII.get(AArch64::ADDXri));
 
     // MOs for a #0 shifted immediate.
diff --git a/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir b/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
deleted file mode 100644
index e88e151bd24..00000000000
--- a/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
+++ /dev/null
@@ -1,54 +0,0 @@
-# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
-
----
-# CHECK-LABEL: name: insert_gprs
-name:            insert_gprs
-legalized:       true
-regBankSelected: true
-
-body:             |
-  bb.0:
-    liveins: %x0
-
-    %0:gpr(s32) = COPY %w0
-
-    %1:gpr(s64) = G_IMPLICIT_DEF
-
-    ; CHECK:  body:
-    ; CHECK: [[TMP:%[0-9]+]] = SUBREG_TO_REG 0, %0, 15
-    ; CHECK: %2 = BFMXri %1, [[TMP]], 0, 31
-    %2:gpr(s64) = G_INSERT %1, %0, 0
-
-    ; CHECK: [[TMP:%[0-9]+]] = SUBREG_TO_REG 0, %0, 15
-    ; CHECK: %3 = BFMXri %1, [[TMP]], 51, 31
-    %3:gpr(s64) = G_INSERT %1, %0, 13
-
-    %x0 = COPY %2
-    %x1 = COPY %3
-...
-
-
----
-# CHECK-LABEL: name: extract_gprs
-name:            extract_gprs
-legalized:       true
-regBankSelected: true
-
-body:             |
-  bb.0:
-    liveins: %x0
-
-    %0:gpr(s64) = COPY %x0
-
-    ; CHECK:  body:
-    ; CHECK: [[TMP:%[0-9]+]] = UBFMXri %0, 0, 31
-    ; CHECK: %1 = COPY [[TMP]].sub_32
-    %1:gpr(s32) = G_EXTRACT %0, 0
-
-    ; CHECK: [[TMP:%[0-9]+]] = UBFMXri %0, 13, 44
-    ; CHECK: %2 = COPY [[TMP]].sub_32
-    %2:gpr(s32) = G_EXTRACT %0, 13
-
-    %w0 = COPY %1
-    %w1 = COPY %2
-...