From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Mon, 17 Jun 2019 13:52:19 +0000 (+0000)
Subject: AMDGPU/GlobalISel: Fix default mapping for non-register operands
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=baa4b8244b7eb151d21b41d4f3c5ba78a0b17027;p=llvm

AMDGPU/GlobalISel: Fix default mapping for non-register operands

Tests will be in future commits when new intrinsics are handled here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363559 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 3d1910384a8..3da487d9124 100644
--- a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -917,7 +917,11 @@ AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {
   OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1);
 
   for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) {
-    unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI);
+    const MachineOperand &MO = MI.getOperand(OpdIdx);
+    if (!MO.isReg())
+      continue;
+
+    unsigned Size = getSizeInBits(MO.getReg(), MRI, *TRI);
     unsigned BankID = Size == 1 ? AMDGPU::VCCRegBankID : AMDGPU::VGPRRegBankID;
     OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(BankID, Size);
   }