From: Michael Liao <michael.hliao@gmail.com>
Date: Sat, 10 Aug 2019 16:15:06 +0000 (+0000)
Subject: [TableGen] Correct the shift to the proper bit width.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=ba58d612702c46c9ef29622f12326487c173d17a;p=llvm

[TableGen] Correct the shift to the proper bit width.

- Replace the previous 32-bit shift with 64-bit one matching `OpInit`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368513 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/TableGen/FixedLenDecoderEmitter/InitValue.td b/test/TableGen/FixedLenDecoderEmitter/InitValue.td
index 27058baa73c..2ed3f1343b4 100644
--- a/test/TableGen/FixedLenDecoderEmitter/InitValue.td
+++ b/test/TableGen/FixedLenDecoderEmitter/InitValue.td
@@ -28,8 +28,19 @@ def bar : Instruction {
     let Inst{15-8} = factor{7-0};
     }
 
+def bax : Instruction {
+    let InOperandList = (ins i32imm:$factor);
+    field bits<16> Inst;
+    field bits<16> SoftFail = 0;
+    bits<33> factor;
+    let factor{32} = 1; // non-zero initial value
+    let Inst{15-8} = factor{32-25};
+    }
+
 }
 
 // CHECK: tmp = fieldFromInstruction(insn, 9, 7) << 1;
 // CHECK: tmp = 0x1;
 // CHECK: tmp |= fieldFromInstruction(insn, 9, 7) << 1;
+// CHECK: tmp = 0x100000000;
+// CHECK: tmp |= fieldFromInstruction(insn, 8, 7) << 25;
diff --git a/utils/TableGen/FixedLenDecoderEmitter.cpp b/utils/TableGen/FixedLenDecoderEmitter.cpp
index 7a6f44b9ab6..cfe06dd4d7f 100644
--- a/utils/TableGen/FixedLenDecoderEmitter.cpp
+++ b/utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -2038,7 +2038,7 @@ populateInstruction(CodeGenTarget &Target, const Record &EncodingDef,
         for (unsigned I = 0; I < OpBits->getNumBits(); ++I)
           if (const BitInit *OpBit = dyn_cast<BitInit>(OpBits->getBit(I)))
             if (OpBit->getValue())
-              OpInfo.InitValue |= 1 << I;
+              OpInfo.InitValue |= 1ULL << I;
 
     unsigned Base = ~0U;
     unsigned Width = 0;