From: Jinsong Ji Date: Mon, 8 Jul 2019 15:24:32 +0000 (+0000) Subject: [PowerPC][NFC]Update testcases using script. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=b8bea16740414c89f409697aeccd84bde83ede4b;p=llvm [PowerPC][NFC]Update testcases using script. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365330 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/PowerPC/power9-moves-and-splats.ll b/test/CodeGen/PowerPC/power9-moves-and-splats.ll index 5ccba80fa4b..d5468902b6b 100644 --- a/test/CodeGen/PowerPC/power9-moves-and-splats.ll +++ b/test/CodeGen/PowerPC/power9-moves-and-splats.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-vsr-nums-as-vr \ ; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu -ppc-vsr-nums-as-vr \ @@ -11,11 +12,12 @@ define <2 x i64> @test1(i64 %a, i64 %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: mtvsrdd v2, r4, r3 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test1: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtvsrdd v2, r3, r4 ; CHECK-BE-NEXT: blr + entry: ; The FIXME below is due to the lowering for BUILD_VECTOR needing a re-vamp ; which will happen in a subsequent patch. @@ -29,11 +31,12 @@ define i64 @test2(<2 x i64> %a) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: mfvsrld r3, v2 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test2: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: blr + entry: %0 = extractelement <2 x i64> %a, i32 0 ret i64 %0 @@ -44,11 +47,12 @@ define i64 @test3(<2 x i64> %a) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: mfvsrd r3, v2 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test3: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mfvsrld r3, v2 ; CHECK-BE-NEXT: blr + entry: %0 = extractelement <2 x i64> %a, i32 1 ret i64 %0 @@ -61,13 +65,14 @@ define <4 x i32> @test4(i32* nocapture readonly %in) { ; CHECK-NEXT: xxpermdi vs0, f0, f0, 2 ; CHECK-NEXT: xxspltw v2, vs0, 3 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test4: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: lfiwzx f0, 0, r3 ; CHECK-BE-NEXT: xxsldwi vs0, f0, f0, 1 ; CHECK-BE-NEXT: xxspltw v2, vs0, 0 ; CHECK-BE-NEXT: blr + entry: %0 = load i32, i32* %in, align 4 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 @@ -82,13 +87,14 @@ define <4 x float> @test5(float* nocapture readonly %in) { ; CHECK-NEXT: xxpermdi vs0, f0, f0, 2 ; CHECK-NEXT: xxspltw v2, vs0, 3 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test5: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: lfiwzx f0, 0, r3 ; CHECK-BE-NEXT: xxsldwi vs0, f0, f0, 1 ; CHECK-BE-NEXT: xxspltw v2, vs0, 0 ; CHECK-BE-NEXT: blr + entry: %0 = load float, float* %in, align 4 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0 @@ -105,7 +111,7 @@ define <4 x i32> @test6() { ; CHECK-NEXT: xxpermdi vs0, f0, f0, 2 ; CHECK-NEXT: xxspltw v2, vs0, 3 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test6: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis r3, r2, .LC0@toc@ha @@ -114,6 +120,7 @@ define <4 x i32> @test6() { ; CHECK-BE-NEXT: xxsldwi vs0, f0, f0, 1 ; CHECK-BE-NEXT: xxspltw v2, vs0, 0 ; CHECK-BE-NEXT: blr + entry: %0 = load i32, i32* @Globi, align 4 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 @@ -130,7 +137,7 @@ define <4 x float> @test7() { ; CHECK-NEXT: xxpermdi vs0, f0, f0, 2 ; CHECK-NEXT: xxspltw v2, vs0, 3 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test7: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis r3, r2, .LC1@toc@ha @@ -139,6 +146,7 @@ define <4 x float> @test7() { ; CHECK-BE-NEXT: xxsldwi vs0, f0, f0, 1 ; CHECK-BE-NEXT: xxspltw v2, vs0, 0 ; CHECK-BE-NEXT: blr + entry: %0 = load float, float* @Globf, align 4 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0 @@ -151,11 +159,12 @@ define <16 x i8> @test8() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v2, v2, v2 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test8: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: xxlxor v2, v2, v2 ; CHECK-BE-NEXT: blr + entry: ret <16 x i8> zeroinitializer } @@ -165,11 +174,12 @@ define <16 x i8> @test9() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v2, 1 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test9: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: xxspltib v2, 1 ; CHECK-BE-NEXT: blr + entry: ret <16 x i8> } @@ -179,11 +189,12 @@ define <16 x i8> @test10() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v2, 127 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test10: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: xxspltib v2, 127 ; CHECK-BE-NEXT: blr + entry: ret <16 x i8> } @@ -193,11 +204,12 @@ define <16 x i8> @test11() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v2, 128 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test11: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: xxspltib v2, 128 ; CHECK-BE-NEXT: blr + entry: ret <16 x i8> } @@ -207,11 +219,12 @@ define <16 x i8> @test12() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v2, 255 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test12: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: xxspltib v2, 255 ; CHECK-BE-NEXT: blr + entry: ret <16 x i8> } @@ -221,11 +234,12 @@ define <16 x i8> @test13() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v2, 129 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test13: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: xxspltib v2, 129 ; CHECK-BE-NEXT: blr + entry: ret <16 x i8> } @@ -235,11 +249,12 @@ define <16 x i8> @test13E127() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v2, 200 ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test13E127: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: xxspltib v2, 200 ; CHECK-BE-NEXT: blr + entry: ret <16 x i8> } @@ -252,7 +267,7 @@ define <4 x i32> @test14(<4 x i32> %a, i32* nocapture readonly %b) { ; CHECK-NEXT: addi r3, r3, 5 ; CHECK-NEXT: stw r3, 0(r5) ; CHECK-NEXT: blr - +; ; CHECK-BE-LABEL: test14: ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: lwz r3, 0(r5) @@ -260,6 +275,7 @@ define <4 x i32> @test14(<4 x i32> %a, i32* nocapture readonly %b) { ; CHECK-BE-NEXT: addi r3, r3, 5 ; CHECK-BE-NEXT: stw r3, 0(r5) ; CHECK-BE-NEXT: blr + entry: %0 = load i32, i32* %b, align 4 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0