From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Wed, 19 Jul 2017 19:17:32 +0000 (+0000)
Subject: [Hexagon] Fix a bug in r308502: post-inc offset is always 0
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=b8ae3835b5c98457635a34854efe187d93fcf3d7;p=llvm

[Hexagon] Fix a bug in r308502: post-inc offset is always 0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308510 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 370af950942..b0101e6f261 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1715,8 +1715,8 @@ bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
   if (!MIa.getOperand(OffsetPosA).isImm() ||
       !MIb.getOperand(OffsetPosB).isImm())
     return false;
-  int OffsetA = OffA.getImm();
-  int OffsetB = OffB.getImm();
+  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
+  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
 
   // This is a mem access with the same base register and known offsets from it.
   // Reason about it.
diff --git a/test/CodeGen/Hexagon/postinc-baseoffset.mir b/test/CodeGen/Hexagon/postinc-baseoffset.mir
new file mode 100644
index 00000000000..69337e92dda
--- /dev/null
+++ b/test/CodeGen/Hexagon/postinc-baseoffset.mir
@@ -0,0 +1,22 @@
+# RUN: llc -march=hexagon -start-before hexagon-packetizer %s -o - | FileCheck %s
+
+# Check that we don't packetize these two instructions together. It happened
+# earlier because "offset" in the post-increment instruction was taken to be 8.
+
+# CHECK: memw(r0+#0) = #-1
+# CHECK: }
+# CHECK: {
+# CHECK: r1 = memw(r0++#8)
+
+--- |
+  define void @fred(i32* %a) { ret void }
+...
+---
+name: fred
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: %r0
+      S4_storeiri_io %r0, 0, -1 :: (store 4 into %ir.a)
+      %r1, %r0 = L2_loadri_pi %r0, 8 :: (load 4 from %ir.a)