From: John Baldwin Date: Mon, 14 Aug 2017 21:49:38 +0000 (+0000) Subject: [MIPS] Implement support for -mstack-alignment. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=b64145c111233b08b76910ae5a7cec8d92195df1;p=llvm [MIPS] Implement support for -mstack-alignment. Summary: This is modeled on the implementation for x86 which stores the command line option in a 'StackAlignOverride' field in MipsSubtarget and then uses this to compute a 'stackAlignment' value in MipsSubtarget::initializeSubtargetDependencies. The stackAlignment() method in MipsSubTarget is renamed to getStackAlignment() and returns the computed 'stackAlignment'. Reviewers: sdardis Reviewed By: sdardis Subscribers: llvm-commits, arichardson Differential Revision: https://reviews.llvm.org/D35874 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310891 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/Mips16FrameLowering.cpp b/lib/Target/Mips/Mips16FrameLowering.cpp index 17dc90ace4a..00f890168e6 100644 --- a/lib/Target/Mips/Mips16FrameLowering.cpp +++ b/lib/Target/Mips/Mips16FrameLowering.cpp @@ -38,7 +38,7 @@ using namespace llvm; Mips16FrameLowering::Mips16FrameLowering(const MipsSubtarget &STI) - : MipsFrameLowering(STI, STI.stackAlignment()) {} + : MipsFrameLowering(STI, STI.getStackAlignment()) {} void Mips16FrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp index 20e6c69c0e7..75adabd5aae 100644 --- a/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/MipsAsmPrinter.cpp @@ -718,7 +718,7 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU()); StringRef FS = TM.getTargetFeatureString(); const MipsTargetMachine &MTM = static_cast(TM); - const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM); + const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM, 0); bool IsABICalls = STI.isABICalls(); const MipsABIInfo &ABI = MTM.getABI(); diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp index 66afe9932b7..4c7e25b4b61 100644 --- a/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -390,7 +390,7 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB, } MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI) - : MipsFrameLowering(STI, STI.stackAlignment()) {} + : MipsFrameLowering(STI, STI.getStackAlignment()) {} void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index e160eac30d8..cd462c75e7a 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -60,7 +60,8 @@ static cl::opt void MipsSubtarget::anchor() {} MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, - bool little, const MipsTargetMachine &TM) + bool little, const MipsTargetMachine &TM, + unsigned StackAlignOverride) : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true), @@ -70,10 +71,10 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false), - HasEVA(false), DisableMadd4(false), HasMT(false), TM(TM), - TargetTriple(TT), TSInfo(), - InstrInfo( - MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))), + HasEVA(false), DisableMadd4(false), HasMT(false), + StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT), + TSInfo(), InstrInfo(MipsInstrInfo::create( + initializeSubtargetDependencies(CPU, FS, TM))), FrameLowering(MipsFrameLowering::create(*this)), TLInfo(MipsTargetLowering::create(TM, *this)) { @@ -157,6 +158,15 @@ MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, if (InMips16Mode && !IsSoftFloat) InMips16HardFloat = true; + if (StackAlignOverride) + stackAlignment = StackAlignOverride; + else if (isABI_N32() || isABI_N64()) + stackAlignment = 16; + else { + assert(isABI_O32() && "Unknown ABI for stack alignment!"); + stackAlignment = 8; + } + return *this; } diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index ef04c931138..0c9688865c1 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -155,6 +155,13 @@ class MipsSubtarget : public MipsGenSubtargetInfo { // Disable use of the `jal` instruction. bool UseLongCalls = false; + /// The minimum alignment known to hold of the stack frame on + /// entry to the function and which must be maintained by every function. + unsigned stackAlignment; + + /// The overridden stack alignment. + unsigned StackAlignOverride; + InstrItineraryData InstrItins; // We can override the determination of whether we are in mips16 mode @@ -186,7 +193,7 @@ public: /// This constructor initializes the data members to match that /// of the specified triple. MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, - const MipsTargetMachine &TM); + const MipsTargetMachine &TM, unsigned StackAlignOverride); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. @@ -295,9 +302,7 @@ public: // really use them if in addition we are in mips16 mode static bool useConstantIslands(); - unsigned stackAlignment() const { - return isABI_N32() || isABI_N64() ? 16 : 8; - } + unsigned getStackAlignment() const { return stackAlignment; } // Grab relocation model Reloc::Model getRelocationModel() const; diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index 4ed06471dd9..2f01b24c237 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -114,11 +114,12 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, getEffectiveCodeModel(CM), OL), isLittle(isLittle), TLOF(llvm::make_unique()), ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), - Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this), + Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, + Options.StackAlignmentOverride), NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", - isLittle, *this), + isLittle, *this, Options.StackAlignmentOverride), Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", - isLittle, *this) { + isLittle, *this, Options.StackAlignmentOverride) { Subtarget = &DefaultSubtarget; initAsmInfo(); } @@ -191,7 +192,7 @@ MipsTargetMachine::getSubtargetImpl(const Function &F) const { // function that reside in TargetOptions. resetTargetOptions(F); I = llvm::make_unique(TargetTriple, CPU, FS, isLittle, - *this); + *this, Options.StackAlignmentOverride); } return I.get(); } diff --git a/test/CodeGen/Mips/stack-alignment.ll b/test/CodeGen/Mips/stack-alignment.ll index 619550fa75b..af0df3eea24 100644 --- a/test/CodeGen/Mips/stack-alignment.ll +++ b/test/CodeGen/Mips/stack-alignment.ll @@ -1,11 +1,15 @@ ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32 +; RUN: llc -march=mipsel -stack-alignment=32 < %s | FileCheck %s -check-prefix=A32-32 ; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=32 ; RUN: llc -march=mips64el -mcpu=mips3 < %s | FileCheck %s -check-prefix=64 ; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64 +; RUN: llc -march=mips64el -mcpu=mips64 -stack-alignment=32 < %s | FileCheck %s -check-prefix=A32-64 ; 32: addiu $sp, $sp, -8 ; 64: daddiu $sp, $sp, -16 +; A32-32: addiu $sp, $sp, -32 +; A32-64: daddiu $sp, $sp, -32 define i32 @foo1() #0 { entry: