From: Amara Emerson <aemerson@apple.com>
Date: Mon, 18 Mar 2019 21:29:21 +0000 (+0000)
Subject: [GlobalISel] Include missing change from r356396
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=b392b2cef2e47d65ea280f6cb4ac475351a90b93;p=llvm

[GlobalISel] Include missing change from r356396

Forgot to add a change to relax some asserts in r356396.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356411 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 81d26e6addb..bc3d805dbd6 100644
--- a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -912,10 +912,8 @@ MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
   }
   case TargetOpcode::COPY:
     assert(DstOps.size() == 1 && "Invalid Dst");
-    assert(SrcOps.size() == 1 && "Invalid Srcs");
-    assert(DstOps[0].getLLTTy(*getMRI()) == LLT() ||
-           SrcOps[0].getLLTTy(*getMRI()) == LLT() ||
-           DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI()));
+    // If the caller wants to add a subreg source it has to be done separately
+    // so we may not have any SrcOps at this point yet.
     break;
   case TargetOpcode::G_FCMP:
   case TargetOpcode::G_ICMP: {