From: Amara Emerson <aemerson@apple.com>
Date: Wed, 10 Apr 2019 23:06:14 +0000 (+0000)
Subject: [AArch64][GlobalISel] Make <2 x p0> = G_BUILD_VECTOR legal.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=b2903912f8d37003d6d506ee33b306ed0a58ee19;p=llvm

[AArch64][GlobalISel] Make <2 x p0> = G_BUILD_VECTOR legal.

The existing isel support already works for p0 once the legalizer accepts it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358144 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/lib/Target/AArch64/AArch64LegalizerInfo.cpp
index 0c1e4b00fa0..9577e26ac8e 100644
--- a/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ b/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -486,6 +486,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
                  {v8s16, s16},
                  {v2s32, s32},
                  {v4s32, s32},
+                 {v2p0, p0},
                  {v2s64, s64}})
       .clampNumElements(0, v4s32, v4s32)
       .clampNumElements(0, v2s64, v2s64)
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir b/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
index 226a469682e..0b69a126f1a 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
@@ -39,3 +39,20 @@ body: |
     $q0 = COPY %2(<2 x s64>)
     RET_ReallyLR
 ...
+---
+name:            legal_v2p0
+body: |
+  bb.0:
+    liveins: $x0, $x1
+    ; CHECK-LABEL: name: legal_v2p0
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[COPY]](p0), [[COPY1]](p0)
+    ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x p0>)
+    ; CHECK: RET_ReallyLR
+    %0:_(p0) = COPY $x0
+    %1:_(p0) = COPY $x1
+    %2:_(<2 x p0>) = G_BUILD_VECTOR %0(p0), %1(p0)
+    $q0 = COPY %2(<2 x p0>)
+    RET_ReallyLR
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir b/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
index 5f3abcc627d..124914233eb 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
@@ -20,6 +20,8 @@
     ret <2 x i64> undef
   }
 
+  define void @test_p0(i64 *%a, i64 *%b) { ret void }
+
 ...
 ---
 name:            test_f32
@@ -30,46 +32,6 @@ regBankSelected: true
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr, preferred-register: '' }
-  - { id: 1, class: fpr, preferred-register: '' }
-  - { id: 2, class: fpr, preferred-register: '' }
-  - { id: 3, class: fpr, preferred-register: '' }
-  - { id: 4, class: fpr, preferred-register: '' }
-  - { id: 5, class: _, preferred-register: '' }
-  - { id: 6, class: _, preferred-register: '' }
-  - { id: 7, class: _, preferred-register: '' }
-  - { id: 8, class: _, preferred-register: '' }
-  - { id: 9, class: _, preferred-register: '' }
-  - { id: 10, class: _, preferred-register: '' }
-  - { id: 11, class: _, preferred-register: '' }
-  - { id: 12, class: _, preferred-register: '' }
-  - { id: 13, class: gpr, preferred-register: '' }
-  - { id: 14, class: gpr, preferred-register: '' }
-  - { id: 15, class: gpr, preferred-register: '' }
-  - { id: 16, class: gpr, preferred-register: '' }
-liveins:
-frameInfo:
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  stackProtector:  ''
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-  localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
-fixedStack:
-stack:
-constants:
 body:             |
   bb.0 (%ir-block.0):
     liveins: $s0, $s1, $s2, $s3
@@ -111,40 +73,6 @@ regBankSelected: true
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
-registers:
-  - { id: 0, class: fpr, preferred-register: '' }
-  - { id: 1, class: fpr, preferred-register: '' }
-  - { id: 2, class: fpr, preferred-register: '' }
-  - { id: 3, class: fpr, preferred-register: '' }
-  - { id: 4, class: fpr, preferred-register: '' }
-  - { id: 5, class: _, preferred-register: '' }
-  - { id: 6, class: _, preferred-register: '' }
-  - { id: 7, class: _, preferred-register: '' }
-  - { id: 8, class: _, preferred-register: '' }
-  - { id: 9, class: gpr, preferred-register: '' }
-  - { id: 10, class: gpr, preferred-register: '' }
-liveins:
-frameInfo:
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  stackProtector:  ''
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-  localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
-fixedStack:
-stack:
-constants:
 body:             |
   bb.0 (%ir-block.0):
     liveins: $d0, $d1, $d2, $d3
@@ -176,42 +104,6 @@ regBankSelected: true
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
-registers:
-  - { id: 0, class: gpr, preferred-register: '' }
-  - { id: 1, class: gpr, preferred-register: '' }
-  - { id: 2, class: gpr, preferred-register: '' }
-  - { id: 3, class: gpr, preferred-register: '' }
-  - { id: 4, class: fpr, preferred-register: '' }
-  - { id: 5, class: _, preferred-register: '' }
-  - { id: 6, class: _, preferred-register: '' }
-  - { id: 7, class: _, preferred-register: '' }
-  - { id: 8, class: _, preferred-register: '' }
-  - { id: 9, class: _, preferred-register: '' }
-  - { id: 10, class: _, preferred-register: '' }
-  - { id: 11, class: _, preferred-register: '' }
-  - { id: 12, class: _, preferred-register: '' }
-liveins:
-frameInfo:
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  stackProtector:  ''
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-  localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
-fixedStack:
-stack:
-constants:
 body:             |
   bb.0 (%ir-block.0):
     liveins: $w0, $w1, $w2, $w3
@@ -247,44 +139,12 @@ regBankSelected: true
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
-registers:
-  - { id: 0, class: gpr, preferred-register: '' }
-  - { id: 1, class: gpr, preferred-register: '' }
-  - { id: 2, class: gpr, preferred-register: '' }
-  - { id: 3, class: gpr, preferred-register: '' }
-  - { id: 4, class: fpr, preferred-register: '' }
-  - { id: 5, class: _, preferred-register: '' }
-  - { id: 6, class: _, preferred-register: '' }
-  - { id: 7, class: _, preferred-register: '' }
-  - { id: 8, class: _, preferred-register: '' }
-liveins:
-frameInfo:
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  stackProtector:  ''
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-  localFrameSize:  0
-  savePoint:       ''
-  restorePoint:    ''
-fixedStack:
-stack:
-constants:
 body:             |
   bb.0 (%ir-block.0):
-    liveins: $x0, $x1, $x2, $x3
+    liveins: $x0, $x1
 
     ; CHECK-LABEL: name: test_i64
-    ; CHECK: liveins: $x0, $x1, $x2, $x3
+    ; CHECK: liveins: $x0, $x1
     ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
     ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
@@ -299,3 +159,32 @@ body:             |
     RET_ReallyLR implicit $q0
 
 ...
+---
+name:            test_p0
+alignment:       2
+exposesReturnsTwice: false
+legalized:       true
+regBankSelected: true
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $x0, $x1
+
+    ; CHECK-LABEL: name: test_p0
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
+    ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]]
+    ; CHECK: $q0 = COPY [[INSvi64gpr]]
+    ; CHECK: RET_ReallyLR implicit $q0
+    %0:gpr(p0) = COPY $x0
+    %1:gpr(p0) = COPY $x1
+    %4:fpr(<2 x p0>) = G_BUILD_VECTOR %0(p0), %1(p0)
+    $q0 = COPY %4(<2 x p0>)
+    RET_ReallyLR implicit $q0
+
+...