From: Ivan Grokhotkov <ivan@espressif.com>
Date: Thu, 6 Dec 2018 06:43:24 +0000 (+0800)
Subject: soc/rtc: reset BBPLL configuration after enabling it
X-Git-Tag: v3.3-beta1~1^2
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=b21ffc8a0ca13b34900fd9f1f055c2fa057717c0;p=esp-idf

soc/rtc: reset BBPLL configuration after enabling it

A workaround to reset BBPLL configuration after light sleep. Fixes the
issue that Wi-Fi can not receive packets after waking up from light
sleep.

Ref. https://github.com/espressif/esp-idf/issues/2711
---

diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c
index 2501373fc4..2c462ed402 100644
--- a/components/soc/esp32/rtc_clk.c
+++ b/components/soc/esp32/rtc_clk.c
@@ -39,10 +39,16 @@
 #define RTC_SLOW_CLK_FREQ_8MD256    (RTC_FAST_CLK_FREQ_8M / 256)
 #define RTC_SLOW_CLK_FREQ_32K       32768
 
+/* BBPLL configuration values */
 #define BBPLL_ENDIV5_VAL_320M       0x43
 #define BBPLL_BBADC_DSMP_VAL_320M   0x84
 #define BBPLL_ENDIV5_VAL_480M       0xc3
 #define BBPLL_BBADC_DSMP_VAL_480M   0x74
+#define BBPLL_IR_CAL_DELAY_VAL      0x18
+#define BBPLL_IR_CAL_EXT_CAP_VAL    0x20
+#define BBPLL_OC_ENB_FCAL_VAL       0x9a
+#define BBPLL_OC_ENB_VCON_VAL       0x00
+
 
 #define APLL_SDM_STOP_VAL_1         0x09
 #define APLL_SDM_STOP_VAL_2_REV0    0x69
@@ -429,6 +435,12 @@ static void rtc_clk_bbpll_enable()
     CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
              RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
              RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
+
+    /* reset BBPLL configuration */
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
 }
 
 /**