From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Sun, 27 Jan 2019 00:53:54 +0000 (+0000)
Subject: GlobalISel: Fix typo in assert messages
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=b1650507d25d28a03f30626843b7b133796597b4;p=llvm

GlobalISel: Fix typo in assert messages

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352301 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 99e768e8ed2..77e130f71d4 100644
--- a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -974,7 +974,7 @@ MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
            "type mismatch in input list");
     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
-           "input scalars do not exactly cover the outpur vector register");
+           "input scalars do not exactly cover the output vector register");
     break;
   }
   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
@@ -1007,7 +1007,7 @@ MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
            "type mismatch in input list");
     assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
                DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
-           "input vectors do not exactly cover the outpur vector register");
+           "input vectors do not exactly cover the output vector register");
     break;
   }
   case TargetOpcode::G_UADDE: {